Cmsemicon CMS80F731 Series, Reference Manual

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CMS80F731x Reference Manual
9.2.2
Timer0/1 Control Register TCON
0x88 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7 TF1: Timer1 counter overflow interrupt flag bit;
1= The Timer1 counter overflows and enters the interrupt service program hardware to
automatically zero;
0= The Timer1 counter has no overflow.
Bit6 TR1: Timer1 operational control bit;
1= Timer1 starts;
0= Timer1 is off.
Bit5 TF0: Timer0 counter overflow interrupt flag bit;
1= The Timer0 counter overflows, entering the interrupt service program hardware to
automatically zero;
0= The Timer0 counter has no overflow.
Bit4 TR0: Timer0 operational control bit;
1= Timer0 starts;
0= Timer0 closes.
Bit3 IE1: External interrupt 1 flag;
1= External interrupt 1 generates an interrupt, and the hardware of the interrupt service
program is automatically cleared;
0= External interrupt 1 did not produce an interrupt.
Bit2 IT1: External interrupt 1 trigger mode control bit;
1= Falling edge trigger;
0= Low level triggering.
Bit1 IE0: External interrupt 0 flag;
1= External interrupt 0 generates an interrupt, and the hardware entering the interrupt service
program is automatically cleared;
0= External interrupt 0 did not produce an interrupt.
Bit0 IT0: External interrupt 0 trigger mode control bit;
1= Falling edge trigger;
0= Low level triggering.