Cmsemicon CMS80F731 Series, Reference Manual

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CMS80F731x Reference Manual
Bit1 T2C1IE: Timer2 compares channel 1 interrupt enable bits;
1= Interrupts are Enabled;
0= Disable Interrupt.
Bit0 T2C0IE: Timer2 compares channel 0 interrupt Enabled bits;
1= Interrupts are Enabled;
0= Disable Interrupt.
If you want to enable the interrupt of Timer2, you also need to turn on the global interrupt enable bit ET2=1 of Timer2 (IE.5=1)
6.4.1.4
P0 Interrupt Control Register P0EXTIE
0xAC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P0EXTIE P07IE P06IE P05IE P04IE P03IE P02IE
P01IE
P00IE
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit0 P0iIE: P0i port interrupt Enabled bits (i=0-7);
1= Interrupts are Enabled;
0= Disable Interrupt.
6.4.1.5
Port P1 Interrupt Control Register P1EXTIE
0xAD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P1EXTIE P17IE P16IE P15IE P14IE P13IE P12IE P11IE P10IE
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit0 P1iIE: P1i interrupt enable bits (i=0-7);
1= Interrupts are Enabled;
0= Disable Interrupt.
6.4.1.6
P2 Interrupt Control Register P2EXTIE
0xAE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P2EXTIE --
-- -- --
P23IE P22IE P21IE P20IE
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit4 -- Reserved, must be 0.
Bit3~Bit0 P2iIE: P2i port interrupt Enabled bits (i=0-3);
1= Interrupts are Enabled;
0= Disable Interrupt.