Cmsemicon CMS80F731 Series, Reference Manual

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CMS80F731x Reference Manual
20.4 SPI-related Registers
20.4.1
SPI Control Register SPCR
0xEC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SPCR -- SPEN SPR2 MSTR CPOL CPHA SPR1 SPR0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 1 0 0
Bit7 -- Reserved, must be 0.
Bit6 SPEN: SPI module enable bit;
1= Enable;
0= Disable.
Bit5 SPR2: The SPI clock frequency selects bit [2].
Bit4 MSTR: SPI mode select bit;
1= Master mode;
0= Slave mode.
Bit3 CPOL: SPI clock polarity select bit;
1= SCLK is high when idle;
0= SCLK is low when idle.
Bit2 CPHA: SPI clock phase select bit.
Bit1~Bit0 SPR<1:0>: SPI Clock Frequency Select Bit [1:0]
(For details of frequency control, see the table below)
The SPR2-SPR0 controls the SPI clock divider
SPR2 SPR1 SPR0 System clock divider
0 0 0 4
0 0 1 8
0 1 0 16
0 1 1 32
1 0 0 64
1 0 1 128
1 1 0 256
1 1 1 512
20.4.2
SPI Data Register SPDR
0xEE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SPDR SPIDATA7 SPIDATA6 SPIDATA5 SPIDATA4 SPIDATA3 SPIDATA2 SPIDATA1 SPIDATA0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit0 SPIDATA<7:0>: Data sent or received by SPI.
Write operation: Write the data that will be sent (the order of sending is from high bit to low bit).
Read operation: Data that has been received.