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CMS80F731x Reference Manual
6.2
External Interrupts
6.2.1
INT0/INT1 Interrupt
The chip supports the 8051 native INT0, INT1 external interrupt, INT0/INT1 can choose to falling edge or low level trigger
interrupt, the relevant control register is TCON. INT0 and INT1 occupy two interrupt vectors.
6.2.2
GPIO Interrupt
Each GPIO pin of the chip supports an external interrupt and can support falling/rising/dual edge interrupts, with the edge
trigger type configured through the Px
N
EICFG registers. For example, configure the P13 port to falling edge interrupt:
P13CFG=0x00; //Set P13 to GPIO
P1TRIS&=0xF7; Set P13 as the input port
P13EICFG=0x02; //Set P13 as a falling edge trigger interrupt
GPIO interrupts occupy a total of 4 interrupt vectors:
Port P0 occupies an interrupt vector 0x003B;
Port P1 occupies an interrupt vector 0x0043;
Port P2 occupies an interrupt vector 0x004B;
Port P5 occupies an interrupt vector 0x0063.
When an interrupt occurs, the interrupt service program can first determine which port triggered the interrupt, and then
process it accordingly.
6.3
Interrupt With Sleep Wake-up
After the system enters sleep mode (STOP wakeable mode), each external interrupt can be set to wake up the system.
INT0/INT1 interrupt wake-up system needs to turn on the corresponding interrupt enable and global interrupt enable, and
the wake-up mode is the falling edge wake-up (INT0/INT1 wake-up mode and interrupt trigger mode select bit IT0/IT1 are
independent).
GPIO interrupt wake-up system, it is recommended to set the corresponding port interrupt trigger edge mode before
entering sleep mode (GPIO wake-up mode is the same as interrupt trigger edge mode, you can choose rising edge/ falling
edge /double edge wake-up), and turn on the corresponding interrupt enable and global interrupt enable.
After the system is woken up by an external interrupt, it first enters the interrupt service program to handle the interrupt
wake task, and after exiting the interrupt service program, the system continues to perform instructions after the hibernation
operation.
