Cmsemicon CMS80F731 Series, Reference Manual

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CMS80F731x Reference Manual
10.3.1.2
Timer2 Interrupt Mask Register T2IE
0xCF Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
T2IE T2OVIE T2EXIE -- -- T2C3IE T2C2IE T2C1IE T2C0IE
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7 T2OVIE: Timer2 overflow interrupt enable bits;
1= Interrupts are Enabled;
0= Disable Interrupt.
Bit6 T2EXIE: Timer2 external loading interrupt enable bits;
1= Interrupts are Enabled;
0= Disable Interrupt.
Bit5~Bit4 --
Reserved, must be 0.
Bit3 T2C3IE: Timer2 compares channel 3 interrupt allowable bits;
1= Interrupts are Enabled;
0= Disable Interrupt.
Bit2 T2C2IE: Timer2 compares channel 2 interrupt enable bits;
1= Interrupts are Enabled;
0= Disable Interrupt.
Bit1 T2C1IE: Timer2 compares channel 1 interrupt enable bits;
1= Interrupts are Enabled;
0= Disable Interrupt.
Bit0 T2C0IE: Timer2 compares channel 0 interrupt Enabled bits;
1= Interrupts are Enabled;
0= Disable Interrupt.
If you want to enable the interrupt of Timer2, you also need to enable the global interrupt enable bit OF TIME2=1 (IE.5=1).
10.3.1.3
Interrupt Priority Control Register IP
0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IP -- PS1 PT2 PS0 PT1 PX1 PT0 PX0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7 --
Reserved, must be 0.
Bit6 PS1: UART1 interrupt priority control bit;
1= Set to High-level Interrupt;
0= Set to low-level interrupt.
Bit5 PT2: TIMER2 interrupt priority control bit;
1= Set to High-level Interrupt;
0= Set to low-level interrupt.
Bit4 PS0: UART0 interrupt priority control bit;
1= Set to High-level Interrupt;
0= Set to low-level interrupt.
Bit3 PT1: TIMER1 interrupt priority control bit;
1= Set to High-level Interrupt;
0= Set to low-level interrupt.
Bit2 PX1: External interrupt 1 interrupt priority control bit;
1= Set to High-level Interrupt;