Cmsemicon CMS80F731 Series, Reference Manual

Page: 131 / 239

www
.mcu.com.cn
132
/
239
Rev.
1.00
CMS80F731x Reference Manual
17.5.13
PWM Cycle Data Register High 8 Bits PWMPnH (n=0-5)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWMPnH
PWMPnH7 PWMPnH6 PWMPnH5 PWMPnH4 PWMPnH3 PWMPnH2 PWMPnH1 PWMPnH0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Registers PWMPnH (n=0-5) Address: F131H, F133H, F135H, F137H, F139H, F13BH.
Bit7~Bit0 PWMPnH<7:0>: The PWM channel n-period data register is 8 bits high.
17.5.14
PWM Compare Data Register Low 8 Bits PWMDnL (n=0-5)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWMDnL
PWMDnL7 PWMDnL6 PWMDnL5 PWMDnL4 PWMDnL3 PWMDnL2 PWMDnL1 PWMDnL0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Registers PWMDnL (n=0-5) Address: F140H, F142H, F144H, F146H, F148H, F14AH.
Bit7~Bit0 PWMDnL<7:0>: PWM channel n compare data (duty cycle data) registers 8 bits lower.
17.5.15
PWM Compare Data Register High 8 BitS PWMDnH (n=0-5)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWMDnH
PWMDnH7 PWMDnH6 PWMDnH5 PWMDnH4 PWMDnH3 PWMDnH2 PWMDnH1 PWMDnH0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Registers PWMDnH (n=0-5) Address: F141H, F143H, F145H, F147H, F149H, F14BH.
Bit7~Bit0 PWMDnH<7:0>: The PWM channel n comparison data (duty cycle data) register is 8 bits higher.
17.5.16
PWM Dead-zone Enable Control Register PWMDTE
F160H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PWMDTE -- -- -- -- -- PWM45DTE PWM23DTE PWM01DTE
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit3 -- Reserved, must be 0.
Bit2 PWM45DTE: PWM4/5 channel dead-zone delay enable bit;
1= Enable;
0= Disable.
Bit1 PWM23DTE: PWM2/3 channel dead-zone delay enable bit;
1= Enable;
0= Disable.
Bit0 PWM01DTE: PWM0/1 channel dead-zone delay enable bit;
1= Enable;
0= Disable.