Cmsemicon CMS80F731 Series, Reference Manual

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CMS80F731x Reference Manual
22.4 UARTn Register
UARTn has the same functionality as the standard 8051 UART. Its Related Registers are: FUNCCR, SBUFn, SCONn,
PCON, IE, IP. The UARTn Data Buffer (SBUFn) consists of 2 independent registers: the transmit and receive registers. The data
written to SBUFn will be set in the UARTn output register and the transmission will begin; The data that reads SBUFn will be
read from the UARTn receive register. The SCON0 register supports bit addressing operations, and the SCON1 registers do
not support bit addressing operations, so be aware when using assembly language. The baud rate is doubled by register PCON
settings.
22.4.1
UART0/1 Baud Rate Selection Register FUNCCR
0x91 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
FUNCCR
-- UART1_CKS2 UART1_CKS1 UART1_CKS0 -- UART0_CKS2 UART0_CKS1 UART0_CKS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Registers in BANK0
Bit7 -- Reserved, must be 0.
Bit6-Bit4 UART1_CKS<2:0>: Timer clock source selection for UART1
000= Overflow clock for Timer1;
001= Overflow clock for Timer4;
010= Overflow clock for Timer2;
011= BRT overflow clock;
Other = Forbidden Access.
Bit3 -- Reserved, must be 0.
Bit2-Bit0 UART0_CKS<2:0>: Timer clock source selection for UART0
000= Overflow clock for Timer1;
001= Overflow clock for Timer4;
010= Overflow clock for Timer2;
011= BRT overflow clock;
Other = Forbidden Access.
22.4.2
UARTn Buffer Register SBUFn
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SBUFn
BUFFERn7 BUFFERn6 BUFFERn5 BUFFERn4 BUFFERn3 BUFFERn2 BUFFERn1 BUFFERn0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value X X X X X X X X
BANK0: Register SBUF0 address 0x99; Register SBUF1 address 0xEB.
Bit7~Bit0 BUFFERn<7:0>: Buffered data registers.
Write: UARTn started sending data.
Read: Reads the received data.