Cmsemicon CMS80F731 Series, Reference Manual

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CMS80F731x Reference Manual
6.4.3.8
P0 port Interrupt Flag Register P0EXTIF
0xB4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P0EXTIF P07IF P06IF P05IF P04IF P03IF P02IF P01IF P00IF
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit0 P0iIF: P0i interrupt flag bit (i=0-7);
1= P0i port produces an interrupt, which requires software clearance;
0= There is no interrupt in the P0i port.
6.4.3.9
Port P1 Interrupt Flag Register P1EXTIF
0xB5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P1EXTIF P17IF P16IF P15IF P14IF P13IF P12IF P11IF P10IF
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit0 P1iIF: P1i interrupt flag bit (i=0-7);
1= P1i port produces an interrupt, which requires software clearance;
0= There is no interrupt in the P1i port.
6.4.3.10
P2 Port Interrupt Flag Bit Register P2EXTIF
0xB6 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P2EXTIF
-- -- -- --
P23IF P22IF P21IF P20IF
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit4 -- Reserved, must be 0.
Bit3~Bit0 P2iIF: P2i interrupt flag bit (i=0-3);
1= P2i port produces an interrupt, which requires software clearance;
0= There is no interrupt in the P2i port.
6.4.3.11
P5 Port Interrupt Flag Bit Register P5EXTIF
0xA7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P5EXTIF -- -- P55IF P54IF P53IF P52IF P51IF P50IF
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit6 -- Reserved, must be 0.
Bit5~Bit0 P5iIF: P5i interrupt flag bit (i=0-5);
1= P5i port produces an interrupt, which requires software clearance;
0= There is no interrupt in the P5i port.