Cmsemicon CMS80F731 Series, Reference Manual

Page: 112 / 239

www
.mcu.com.cn
113
/
239
Rev.
1.00
CMS80F731x Reference Manual
12.3 Interrupt With Sleep Wake-up
The LSE timer can enable or disable interrupts via LSECON registers, setting high/low priority via EIP3 registers, where
the relevant bits are described as following.
0xBB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EIP3 -- -- -- -- PLVD PLSE -- --
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit5 --
Reserved, must be 0.
Bit4 PTOUCH TOUCH interrupt priority control bit;
1= Set to High-level Interrupt;
0= Set to low-level interrupt.
Bit3 PLVD: LVD interrupt priority control bit;
1= Set to High-level Interrupt;
0= Set to low-level interrupt.
Bit2 PLSE: LSE interrupt priority control bit;
1= Set to High-level Interrupt;
0= Set to low-level interrupt.
Bit1~Bit0 --
Reserved, must be 0.
When the count value of the LSE timer is equal to the timer value, the off flag bit LSEIF in the timer
is set to 1
. If the global
interrupt is enabled (EA=1) and the LSE timer interrupt is enabled (LSEIE=1), the CPU executes the interrupt service program.
Using LSE timed interrupt wake-up sleep mode, you need to enable LSEEN, LSECNT, LSEWUEN before hibernation,
and set the post-hibernation state to wake up time. If the global interrupt enable and LSE interrupt enable are turned on before
hibernation, after hibernation wakes up, the interrupt service program is executed first, and the next instruction of the
hibernation instruction is executed after the interrupt returns.
{ LSECRH[7:0]
，
LSECRL[7:0]}