Cmsemicon CMS80F731 Series, Reference Manual

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CMS80F731x Reference Manual
10.2 Related Registers
10.2.1
Timer2 Control Register T2CON
0xC8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
T2CON
T2PS I3FR
CAPES
T2R1 T2R0 T2CM T2I1 T2I0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7 T2PS: Timer2 clock prescaler selection bit;
1= Fsys/24;
0= Fsys/12.
Bit6 I3FR: Capture channel 0 input one-edge selection with comparison interrupt moment
selection bit;
Capture channel 0 mode:
1= Rising edge capture to RLDL/RLDH registers;
0= The falling edge is captured to the RLDL/RLDH register.
Compare channel 0 modes:
1= TL2/TH2 and RLDL/RLDH never wait until the same moment to produce an
interrupt;
0= TL2/TH2 and RLDL/RLDH are interrupted from the moment of equality to
inequality;
Bit5 CAPES: Capture channels 1-3 input one-edge edge selection (in effect for capture
channels 1-3).
0= The rising edge is captured to the CCL1/CCH1-CCL3/CCH3 registers;
1= The falling edge is captured to the CCL1/CCH1-CCL3/CCH3 registers.
Bit4~Bit3 T2R<1:0>: Timer2 Load mode select bit;
0x= Reloading is prohibited;
10= Loading mode 1: Automatically Reload when Timer2 overflows;
11= Loading mode 2: Reload on the falling edge of the T2EX pin.
Bit2 T2CM: Comparison mode selection;
1= Comparison mode 1;
0= Compare mode 0.
Bit1~Bit0 T2I<1:0>: Timer2 clock input select bit;
00= Timer2 stops;
01= Division of the system clock (selected by T2PS control crossover);
10= External pin T2 for event input (event count mode);
11= External pin T2 is the gating input (gating timing mode).
10.2.2
Timer2 Data Register Low bit TL2
0xCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TL2
TL27 TL26 TL25 TL24 TL23 TL22 TL21 TL20
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit0 TL2<7:0>: Timer 2 low bit data register (also as counter low bit).