Cmsemicon CMS80F731 Series, Reference Manual

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CMS80F731x Reference Manual
12.
LSE Timer(LSE_Timer)
12.1 Overview
The LSE timer is a clock source from an external low-speed clock LSE, a 16-bit up-counting timer. When using the LSE
timer function, you should first set the LSE module to enable, wait for the LSE clock to stabilize (about 1.5s), and then set the
LSE count enable. The counter adds 1 to the rising edge of the LSE clock, and when the count value is equal to the timing
value, the interrupt flag LSECON[0] is set to 1, and the counter starts counting from 0 again. The timing value is set by
registers {LSECRH[7:0], LSECRL[7:0]}.
If the LSE timing function is configured before hibernation, the LSE oscillator and LSE timer can continue to operate
without being affected while the chip is asleep. If the LSE timed wake function is set before sleep, the system will wake up
when the count value is equal to the timed value.
12.2 Related Registers
12.2.1
LSE Timer Data Register Low 8 Bit LSECRL
F694H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
LSECRL LSED7 LSED6 LSED5 LSED4 LSED3 LSED2 LSED1 LSED0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 1 1 1 1 1 1 1 1
Bit7~Bit0 LSED<7:0>: LSE timing/wake-up time data is 8 bits lower.
12.2.2
LSE Timer Data Registers are 8 Bits High LSECRH
F695H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
LSECRH LSED15 LSED14 LSED13 LSED12 LSED11 LSED10 LSED9 LSED8
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 1 1 1 1 1 1 1 1
Bit7~Bit0 LSED<15:8>: LSE timing/wake-up time data is 8 bits higher.