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CMS80F731x Reference Manual
21.3.3
I2C Slave Address Register
The slave address register consists of 8 bits: 7 bits of address (A6-A0) and receive/transmit bits R/S. The R/S bit determines
whether the next operation is to receive (1) or send (0).
Master mode slave address register I2CMSA
0xF4
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
I2CMSA
SA6
SA5
SA4
SA3
SA2
SA1
SA0
R/S
R/W
R
R
R
R
R
R
R
R
Reset value
0
0
0
0
0
0
0
0
Bit7~Bit1
AT<6:0>:
I2C Master mode slave address.
Bit0
R/S:
I2C Master mode after sending slave address after receiving/sending status selection
bits;
1=
Receive data after correct addressing;
0=
The data is sent after correct addressing.
21.3.4
I2C Master Mode Transmit and Receive Data Registers
The transmit data register consists of eight data bits that will be sent on the bus on the next send or burst send operation,
the first of which is MD7 (MSB).
Master mode data cache register I2CMBUF
0xF6
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
I2CMBUF
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0
0
0
0
0
0
0
0
Bit7~Bit0
MD<7:0>:
Send/receive data in I2C master mode.
