Cmsemicon CMS80F731 Series Reference Manual Download Page 23

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CMS80F731x Reference Manual

address

F092H

P22EICFG

P22 port interrupt control register

F093H

P23EICFG

P23 interrupt control register

F0B8H

P50EICFG

P50 port interrupt control register

F0B9H

P51EICFG

P51 interrupt control register

F0BAH

P52EICFG

P52 port interrupt control register

F0BBH

P53EICFG

P53 port interrupt control register

F0BCH

P54EICFG

P54-port interrupt control register

F0BDH

P55EICFG

P55 port interrupt control register

F0C0H

PS_INT0

External interrupt 0 input port allocation register

F0C1H

PS_INT1

External interrupt 1 input port allocation register

F0C2H

PS_T0

Timer0 external clock input port assignment register

F0C3H

PS_T0G

Timer0 gated input port assignment register

F0C4H

PS_T1

Timer1 external clock input port assignment register

F0C5H

PS_T1G

Timer1 gated input port assignment register

F0C6H

PS_T2

Timer2 external event or gated input port assignment
register

F0C7H

PS_T2EX

Timer2 drops along the autoreload input port allocation
register

F0C8H

PS_CAP0

The Timer2 input captures channel 0 port assignment
registers

F0C9H

PS_CAP1

The Timer2 input captures the channel 1 port assignment
register

F0CAH

PS_CAP2

The Timer2 input captures the channel 2 port assignment
register

F0CBH

PS_CAP3

The Timer2 input captures the channel 3 port assignment
register

F0CCH

PS_ADET

The ADC's external trigger input port allocates registers

F120H

PWMCON

PWM control registers

F121H

PWMOE

PWM output enable register

F122H

PWMPINV

PWM output polarity selection register

F123H

PWM01PSC

PWM0/1 clock prescaler control register

F124H

PWM23PSC

PWM2/3 clock prescale control register

F125H

PWM45PSC

PWM4/5 clock prescale control register

F126H

PWMCNTE

The PWM count starts the control register

F127H

PWMCNTM

PWM counting mode select register

F128H

PWMCNTCLR

PWM counter clears control registers

F129H

PWMLOADEN

PWM loads the enable control register

F12AH

PWM0DIV

PWM0 clock divider control register

F12BH

PWM1DIV

PWM1 clock divider control register

F12CH

PWM2DIV

PWM2 clock divider control register

F12DH

PWM3DIV

PWM3 clock divider control register

F12EH

PWM4DIV

PWM4 clock divider control register

F12FH

PWM5DIV

PWM5 clock divider control register

F130H

PWMP0L

The PWM0 cycle data register is 8 bits lower

F131H

PWMP0H

The PWM0 cycle data register is 8 bits high

F132H

PWMP1L

The PWM1 cycle data register is 8 bits lower

F133H

PWMP1H

The PWM1 cycle data register is 8 bits high

Summary of Contents for CMS80F731 Series

Page 1: ...damage to the company The name of Cmsemicron Limited and logo are both trademarks of our company Our company preserve the rights to further elaborate on the improvements about products function relia...

Page 2: ...External Special Function Register XSFR 22 3 Reset 29 3 1 Power on Reset 29 3 2 External Reset 31 3 3 LVR Low voltage Reset 31 3 4 Watchdog Reset 32 3 5 Software Reset 32 3 6 CONFIG Status Protection...

Page 3: ...errupt Flag Bit Register T2IF 54 6 4 3 3 Peripheral Interrupt Flag Bit Register EIF2 55 6 4 3 4 SPI Interrupt Flag Bit Register SPSR 56 6 4 3 5 I2C Master Mode Interrupt Flag Registers I2CMCR I2CMSR 5...

Page 4: ...4 3 T0 Mode 2 8 bit Auto reload Timing Counting Mode 84 9 4 4 T0 Mode 3 Two Separate 8 bit Timers Counters 84 9 5 Timer1 Working Mode 85 9 5 1 T1 Mode 0 13 bit Timing Counting Mode 85 9 5 2 T1 Mode 1...

Page 5: ...103 11 2 4 Timer4 Data Register Low Bit TL4 103 11 2 5 Timer4 Data Register High Bit TH4 103 11 3 Timer3 4 Interrupt 104 11 3 1 Interrupt Mask Register EIE2 104 11 3 2 Interrupt Priority Control Regi...

Page 6: ...tic 123 17 3 Port Configuration 123 17 4 Feature Description 124 17 4 1 Functional Block Diagram 124 17 4 2 Edge Alignment 125 17 4 3 Complementary Model 126 17 4 4 Synchronous Mode 127 17 5 PWM relat...

Page 7: ...8 3 13 COM4 Corresponding SEG Data Register LEDC4DATAn n 0 1 141 18 3 14 COM5 Corresponding SEG Data Register LEDC5DATAn n 0 1 141 18 3 15 COM6 Corresponding SEG Data Register LEDC6DATAn n 0 1 141 18...

Page 8: ...rror 173 20 7 SPI Clock Control Logic 175 20 7 1 SPI Clock Phase and Polarity Control 175 20 7 2 SPI Transfer Format 175 20 7 3 CPHA 0 Transfer Format 175 20 7 4 CPHA 1 Transfer Format 176 20 8 SPI Da...

Page 9: ...de 0 Synchronous Mode 206 22 6 2 Mode 1 8 Bit Asynchronous Mode Variable Baud Rate 206 22 6 3 Mode 2 9 Bit Asynchronous Mode Fixed Baud Rate 207 22 6 4 Mode 3 9 Bit Asynchronous Mode Variable Baud Rat...

Page 10: ...t Flag Bit Register EIF2 222 24 Touch Module TOUCH 223 24 1 Touch Module Usage Considerations 223 25 Flash Memory 224 25 1 Overview 224 25 2 Related Registers 225 25 2 1 Flash Protect Lock Register ML...

Page 11: ...their default values The following program demonstrates how to define a reset vector in FLASH Example Define a reset vector ORG 0000H System reset vector LJMP START ORG 0010H The user program starts...

Page 12: ...rate a watchdog reset Other values Invalid For example after the chip is powered on and booted from the BOOT area use the software reset method to switch to the APROM area and the configuration is as...

Page 13: ...starts at 08H of the RAM address The value of the SP can be modified and if the stack region is set to start 0xC0 the value of the SP needs to be set to 0xBF after the system reset Operations that aff...

Page 14: ...n operations determined by ID1 ID0 0 DPTR related directives do not affect DPTR itself Bit3 Bit1 Reserved must be 0 Bit0 SALT Data pointer selection bit 1 Select DPTR1 0 Select DPTR0 1 8 Program Statu...

Page 15: ...nditional jump instruction is encountered and the jump condition is met the next instruction read during the execution of the current instruction will be discarded and an empty instruction operation c...

Page 16: ...PC is used as an address pointer The PC is a 16 bit program counter so the address space that can be addressed is 64KB but this chip only has 16K bytes of program storage space The FLASH space allocat...

Page 17: ...ce allocation block diagram is shown in the following figure 03FFH Data FLASH 1KB 0000H The read write and erase operations of the Data FLASH memory are implemented through the FLASH control interface...

Page 18: ...to 2FH behind the register bank form a bit addressable storage space and the RAM units in this area can operate either byte byte or directly on each bit in the unit With the remaining 80 storage unit...

Page 19: ...0000H XRAM XSFR spatial access operates through DPTR data pointers which consist of two sets of pointers DPTR0 DPTR1 selected by the DPS registers For example through movx indirection operations the a...

Page 20: ...9 2 A 3 B 4 C 5 D 6 E 7 F 0xF8 PCRCDL PCRCDH MLOCK MADRL MADRH MDATA MCTRL 0xF0 B I2CSADR I2CSCR I2CSBUF I2CMSA I2CMCR I2CMBUF I2CMTP 0xE8 ADCON2 SCON1 SBUF1 SPCR SPSR SPDR SSCR 0xE0 ACC TL4 TH4 0xD8...

Page 21: ...configuration register F006H P06CFG P06 port configuration register F007H P07CFG P07 port configuration register F009H P0OD P0 port open drain control register F00AH P0UP P0 port pull up resistor cont...

Page 22: ...drain control register F05AH P5UP P5 port pull up resistor control register F05BH P5RD P5 port pull down resistor control register F05CH F05DH P5SR P5 port slope control register F05EH P5DS P5 port d...

Page 23: ...mer2 input captures the channel 1 port assignment register F0CAH PS_CAP2 The Timer2 input captures the channel 2 port assignment register F0CBH PS_CAP3 The Timer2 input captures the channel 3 port ass...

Page 24: ...ts lower to the data register F147H PWMD3H PWM3 compares the data registers 8 bits higher F148H PWMD4L PWM4 compares 8 bits lower to the data register F149H PWMD4H PWM4 compares the data registers 8 b...

Page 25: ...rt assignment register F69DH PS_SDA IIC data input port assignment registers F69EH PS_RXD1 UART1 data input port assignment register F69FH PS_RXD0 UART0 data input port assignment register F6D0H KEYCO...

Page 26: ...ister matrix driver LED3 dot matrix drive displays data registers dot matrix drive F748H LEDC2DATA0 LED4DATA LED COM2 corresponding the SEG7 SEG0 data register matrix driver LED4 dot matrix drive disp...

Page 27: ...0 SCAN1WH LED SEG7 SEG0 enable register 0 matrix drive LED dot matrix drive first stage configuration register 8 bits high dot matrix drive F762H LEDSEGEN1 SCAN1WL LED SEG15 SEG8 enable register 1 mat...

Page 28: ...ero and the program will run from the reset vector 0000H after the reset is completed Any kind of reset situation requires a certain response time and the system provides a perfect reset process to en...

Page 29: ...reset control bit 1 Perform a system software reset write 0 clear after reset 0 Bit6 PORF Power on reset marker 1 The system resets the system at power on write 0 clear do not need TA to write timing...

Page 30: ...r power on reset The external reset pin NRST and its pull up resistor enable configured via CONFIG 3 3 LVR Low voltage Reset A low voltage reset LVR function is integrated inside the chip and when the...

Page 31: ...d by the system clock and the timing base period of the WDT counter is Tsys After the WDT overflow resets the CPU with all registers the program executes immediately after 1 Tsys from 0000H The WDT re...

Page 32: ...the value of the register is not a fixed code force the LSI oscillator and HSI oscillator to be enabled and the system clock switches to the LSI clock if after 12 Fixed_Clock sampling or 3 LSI clock s...

Page 33: ...ration register with the programming tool and host computer software or through the user register configuration follow the procedure to set the relevant register as detailed below When using external...

Page 34: ...set value 0 0 0 0 0 0 0 0 Bit7 Forbidden Access Bit6 Bit5 Reserved must be 0 Bit4 SALT System clock configuration selection 1 Based on the clock source configured CKSEL 2 0 0 The clock source configur...

Page 35: ...R R RW R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 LSI_F Low speed internal steady state bit 1 Stability 0 Not stable Bit6 LSE_F Steady state bit of low speed external crystal 1 Stability 0 Not stabl...

Page 36: ...tware can clear 0 Bit0 SCMSTA Stop status bit read only 1 Indicates oscillation stopping 0 Shutdown recovery Note 1 Both SCMIF and SCMSTA can reflect the state of the HSE LSE system clock The biggest...

Page 37: ...select bit of Timer0 0 Fsys 12 1 Fsys 4 Bit2 Bit0 Reserved must be 1 UART0 1 baud rate selection register FUNCCR 0x91 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 FUNCCR UART1_CKS2 UART1_CKS1 UART1_CKS0 UA...

Page 38: ...ration after judging the position of the error flag The system clock switching steps are shown in the following figure Chip Power On Chip configuration completes Clock source selection Clock stability...

Page 39: ...nitors the system clock HSE LSE every 4ms and the duty cycle of the TSCM is 1 1 When TSCM is high SCM performs oscillation stop monitoring of HSE LSE TSCM processes the monitoring results during low l...

Page 40: ...e 0 0 0 0 0 0 0 0 Bit7 SMOD0 UART0 baud rate multiplier 0 UART0 baud rate is normal 1 The UART0 baud rate doubles Bit6 SMOD1 UART1 baud rate multiplier 0 UART1 baud rate is normal 1 The UART1 baud rat...

Page 41: ...00V 0010 2 00V 1010 3 70V 0011 2 40V 1011 2 00V 0100 2 00V 1100 4 00V 0101 2 70V 1101 4 30V 0110 2 00V 1110 2 00V 0111 3 00V 1111 2 00V Bit3 LVDEN LVD enable 0 Prohibited 1 Enable Bit2 Reserved must b...

Page 42: ...E timed wake up To wake up by LSE timing the LSE module enable count enable and timed wake function must be turned on before entering hibernation and the hibernation state must be set to wake up time...

Page 43: ...p current obtained by the test is not the real sleep power consumption It is recommended to turn off debug mode after the development of the sleep wake function is completed in debug mode and then res...

Page 44: ...pt 12 0x0063 13 13 0x006B 14 14 0x0073 15 Timer3 Timer 3 interrupt 15 0x007B 16 Timer4 Timer 4 interrupt 16 0x0083 17 LED LED dot matrix scanning is interrupted 17 0x008B 18 PWM PWM interrupt 18 0x009...

Page 45: ...x0063 When an interrupt occurs the interrupt service program can first determine which port triggered the interrupt and then process it accordingly 6 3 Interrupt With Sleep Wake up After the system en...

Page 46: ...0 0 0 0 0 Bit7 SHE Global interrupt enable bits 1 Enable all unblocked interrupts 0 Disable all interrupts Bit6 ES1 UART1 interrupt enable bit 1 EnableS UART1 interrupt 0 Disable UART1 Interrupt Bit5...

Page 47: ...pts 0 Disable all PWM interrupts Bit2 Reserved must be 0 Bit1 ET4 Timer4 interrupt enable bit 1 Enable Timer4 interrupts 0 Disable Timer4 Interrupt Bit0 ET3 Timer3 interrupt enable bit 1 Enable Timer3...

Page 48: ...W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 Bit0 P0iIE P0i port interrupt Enabled bits i 0 7 1 Interrupts are Enabled 0 Disable Interrupt 6 4 1 5 Port P1 Interrupt Control Register P1EXTIE 0xAD Bit...

Page 49: ...ster P5EXTIE 0x9C Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P5EXTIE P55IE P54IE P53IE P52IE P51IE P50IE R W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 Bit6 Reserved must be 0 Bit5...

Page 50: ...upt priority control bit 1 Set to High level Interrupt 0 Set to low level interrupt Bit2 PX1 External interrupt 1 interrupt priority control bit 1 Set to High level Interrupt 0 Set to low level interr...

Page 51: ...I2C interrupt priority control bit 1 Set to High level Interrupt 0 Set to low level interrupt Bit5 PWDT WDT interrupt priority control bit 1 Set to High level Interrupt 0 Set to low level interrupt B...

Page 52: ...Reset value 0 0 0 0 0 0 0 0 Bit7 Bit5 Reserved must be 0 Bit4 PTOUCH TOUCH interrupt priority control bit 1 Set to High level Interrupt 0 Set to low level interrupt Bit3 PLVD LVD interrupt priority c...

Page 53: ...xternal interrupt 1 generates an interrupt the hardware is automatically cleared when entering the interrupt service program and the software can also be cleared 0 External interrupt 1 did not produce...

Page 54: ...ndicator bit read only 1 SPI generates an interrupt this bit is automatically cleared after the specific interrupt flag is cleared 0 The SPI did not produce an interrupt Bit6 I2CIF I2C global interrup...

Page 55: ...t be 0 Bit0 SSCEN SPI master mode NSS output control bit 1 When the SPI is idle the NSS output is high 0 NSS output registers the contents of the SSCR 6 4 3 5 I2C Master Mode Interrupt Flag Registers...

Page 56: ...0 Not received The relevant status bits for I2C slave mode are also interrupt flag bits Note The I2C Master mode interrupt shares the same interrupt vector 00ABH as the slave mode interrupt 6 4 3 7 U...

Page 57: ...i 0 7 1 P1i port produces an interrupt which requires software clearance 0 There is no interrupt in the P1i port 6 4 3 10 P2 Port Interrupt Flag Bit Register P2EXTIF 0xB6 Bit7 Bit6 Bit5 Bit4 Bit3 Bit...

Page 58: ...itten to zero to the flag bit but requires reading writing other registers to clear the flag bit For example if the transmission completion flag bit SPISIF in the SPI interrupt flag register is set to...

Page 59: ...transmit completion flag bit SPISIF in the SPI interrupt flag register in debug mode Set the port and interrupt enable SPDR 0x56 Send SPDR data delay void SPI_int void interrupt SPI_VECTOR SPI interr...

Page 60: ...Tx pin as an analog input the user must ensure that the bits in the PxTRIS register remain in the set 0 state I O pins configured as analog inputs are always read as 0 Registers related to PORTx ports...

Page 61: ...3 PxUP2 PxUP1 PxUP0 R W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Register P0UP Address F00AH Register P1UP Address F01AH Register P2UP Address F02AH Register P5UP address F05AH Bit7...

Page 62: ...t Selects Register PxDS Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PxDS PxDS7 PxDS6 PxDS5 PxDS4 PxDS3 PxDS2 PxDS1 PxDS0 R W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Register P0DS Addre...

Page 63: ...T0G T1G T2EX GPIO ANA MISO CC2 PG2 TXD1 RXD1 P03 T0 T1 T2 GPIO ANA NSS NSSO0 CC3 PG3 TXD1 RXD1 P04 GPIO ANA TXD0 NSS NSSO1 PG4 TXD1 RXD1 P05 GPIO ANA RXD0 NSS NSSO2 PG5 TXD1 RXD1 P06 MOQ INT0 GPIO AN...

Page 64: ...COM3 LED3 AN3 TK3 P04 SEG0 COM4 LED4 AN4 TK4 P05 SEG1 COM5 LED5 AN5 TK5 P06 SEG2 COM6 LED6 AN6 TK6 P07 SEG3 COM7 LED7 AN7 TK7 P10 SEG4 LED8 AN8 TK8 P11 SEG5 AN9 TK9 P12 SEG6 AN10 TK10 P13 SEG7 AN11 TK...

Page 65: ...3 The Port Input Function Allocation Registers Inside the chip there are digital functions with only the input state such as INT0 INT1 etc this type of digital input function is independent of the po...

Page 66: ...s T1 functions the P03 configuration is valid and the P13 configuration is invalid 2 The input function assignment structure allows multiple input functions to be assigned to the same port For example...

Page 67: ...er PS_SDA F69DH SDA IIC data input port assignment registers PS_RXD1 F69EH RXD1 UART1 data input port assignment register PS_RXD0 F69FH RXD0 UART0 data input port assignment register Communication inp...

Page 68: ...nction you need to set the value of the register to 0x00 2 The input of the multiplexing function is relatively independent of the structure of the port s external interrupt GPIO interrupt and port in...

Page 69: ...as a synchronous output function multiple pins can be selected as RXD0 1 outputs at the same time 9 When the SPI s SCLK is used as the clock input of the slave it needs to be selected by the port all...

Page 70: ...en the system is running to an unknown state the watchdog can be used to reset the system thereby avoiding the system from entering an indefinite dead loop Watchdog overflow reset is detailed in the R...

Page 71: ...ed by WDCON no other instructions can be inserted in the middle MOV TA 0AAH MOV TA 055H ORL WDCON 01H 8 2 2 Watchdog Overflow Control Register CKCON 0x8E Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CKCON...

Page 72: ...PI interrupt enable bit 1 Enable SPI interrupts 0 Prohibited SPI Interrupt Bit6 I2CIE I2C interrupt enable bit 1 Enable I2C interrupts 0 Disable I2 C interrupt Bit5 WDTIE WDT interrupt enable bit 1 En...

Page 73: ...interrupt Bit5 PWDT WDT interrupt priority control bit 1 Set to High level Interrupt 0 Set to low level interrupt Bit4 PADC ADC interrupt priority control bit 1 Set to High level Interrupt 0 Set to l...

Page 74: ...4 0 form a 13 bit timer counter 1 0 1 THx 7 0 TLx 7 0 form a 16 bit timer counter 2 1 0 TLx 7 0 consists of an 8 bit auto reload timer counter that is reloaded from THx 3 1 1 TL0 TH0 are two 8 bit tim...

Page 75: ...imer 1 timing count select bits 1 Count 0 Timing Bit5 Bit4 T1M 1 0 Timer 1 mode select bit 00 Mode 0 13 bit timer counter 01 Mode 1 16 bit timer counter 10 Mode 2 8 bit automatic reload timer counter...

Page 76: ...g the interrupt service program hardware to automatically zero 0 The Timer0 counter has no overflow Bit4 TR0 Timer0 operational control bit 1 Timer0 starts 0 Timer0 closes Bit3 IE1 External interrupt...

Page 77: ...W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 Bit0 TH0 7 0 Timer 0 high bit data register also as counter high bit 9 2 5 Timer1 Data Register Low Bit TL1 0x8B Bit7 Bit6 Bit5 Bit4 Bit3 Bit...

Page 78: ...0M R W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 1 1 1 Bit7 Bit5 WTS 2 0 WDT overflow time selection bits 000 217 Tsys 001 218 Tsys 010 219 Tsys 011 220 Tsys 100 221 Tsys 101 222 Tsys 110...

Page 79: ...1 UART1 interrupt enable bit 1 Enable UART1 interrupt 0 Disable UART1 Interrupt Bit5 ET2 TIMER2 Global interrupt Enable bits 1 Enable timer2 all interrupts 0 Disable all TIMER2 interrupts Bit4 ES0 UAR...

Page 80: ...t 1 Set to High level Interrupt 0 Set to low level interrupt Bit4 PS0 UART0 interrupt priority control bit 1 Set to High level Interrupt 0 Set to low level interrupt Bit3 PT1 TIMER1 interrupt priority...

Page 81: ...0 Timer0 closes Bit3 IE1 External interrupt 1 flag 1 External interrupt 1 generates an interrupt the hardware is automatically cleared when entering the interrupt service program and the software can...

Page 82: ...an external pin T0G for pulse width measurements The 13 bit register consists of TH0 and TL0 low 5 bits TL0 high 3 bits should be ignored Timer0 Mode 0 block diagram is shown in the following figure...

Page 83: ...and TH0 to two independent counters The logic of timer 0 mode 3 is shown in the following figure TL0 can operate as a timer or counter and use the control bits of timer 0 such as CT0 TR0 GATE0 and TF0...

Page 84: ...an external pin T1G for pulse width measurements The 13 bit register consists of TH1 8 bits and TL1 low 5 bits TL1 high three bits should be ignored Timer1 Mode 0 block diagram is shown in the followi...

Page 85: ...e overflow from TL1 not only makes TF1 1 but also reloads the contents of TH1 from software to TL1 The value of TH1 remains unchanged during Reloading The Timer1 mode 2 block diagram is shown in the f...

Page 86: ...pulse width measurement etc 10 1 Overview Block diagram of timer 2 with additional compare capture reload register functions is shown in the following figure T2EX CLK Sync Compare T2EXIF TF2 12 2 0 1...

Page 87: ...s 1 3 input one edge edge selection in effect for capture channels 1 3 0 The rising edge is captured to the CCL1 CCH1 CCL3 CCH3 registers 1 The falling edge is captured to the CCL1 CCH1 CCL3 CCH3 regi...

Page 88: ...Register High Bit RLDH 0xCB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RLDH RLDH7 RLDH6 RLDH5 RLDH4 RLDH3 RLDH2 RLDH1 RLDH0 R W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 Bit0 RLDH...

Page 89: ...R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 Bit0 CCH2 7 0 Timer 2 compares captures channel 2 register bits 10 2 10 Timer2 Compares Captures Channel 3 Register Low bit CCL3 0xC6 Bit7...

Page 90: ...ure Compare Prohibited 01 The capture operation is triggered on the rising or falling edge of channel 2 CAPES selection 10 Comparison mode enable 11 The capture operation is triggered when writing CCL...

Page 91: ...r IE 0xA8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IE SHE ES1 ET2 ES0 ET1 EX1 ET0 EX0 R W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 SHE Global interrupt enable bits 1 Enable all...

Page 92: ...nabled 0 Disable Interrupt Bit0 T2C0IE Timer2 compares channel 0 interrupt Enabled bits 1 Interrupts are Enabled 0 Disable Interrupt If you want to enable the interrupt of Timer2 you also need to enab...

Page 93: ...externally loaded flag bits 1 The T2EX port of Timer2 generates a falling edge which requires software clearance 0 Bit5 Bit4 Reserved must be 0 Bit3 T2C3IF Timer2 Compare Capture Channel 3 Flag Bits 1...

Page 94: ...ring channel 0 can choose to compare the moment when the interrupt occurred and if an interrupt is generated the interrupt flag T2C0IF of the comparison channel 0 is set to 1 When I3FR 0 TL2 TH2 and R...

Page 95: ...and TL2 is incremented every 12 clock cycles or every 24 clock cycles 10 4 2 Reload Mode The reload mode of timer 2 is selected by the T2R0 and T2R1 bits of register T2CON as shown in the reload block...

Page 96: ...ction is often used to measure pulse width 10 4 4 Event Counting Mode When Timer2 is used as an event counting function the timer counter adds 1 to the falling edge of the external input pin T2 The ex...

Page 97: ...he comparison register is compared to the count value of the timer and if the count value in the data register matches the stored value a jump in the output signal is generated on the corresponding po...

Page 98: ...aptively determines the output signal transition If mode 1 is enabled the software writes to the corresponding output register of the CCx port and the new value does not appear on the output pin until...

Page 99: ...or a negative transaction triggers capture operation on capture channel 0 depends on the I3FR bit of T2CON I3FR 0 negative transaction trigger capture I3FR 1 positive transaction trigger capture Wheth...

Page 100: ...tes a capture operation and the value written is independent of this function After the write instruction is executed the contents of timer 2 are latched into the corresponding capture register In cap...

Page 101: ...s of an 8 bit auto reload timer that is reinstalled from THx 3 1 1 TL3 TH3 are two 8 bit timers and Timer4 stop counting 11 2 Related Registers 11 2 1 Timer3 4 Control Register T34MOD 0xD2 Bit7 Bit6 B...

Page 102: ...W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 Bit0 TH3 7 0 Timer 3 high bit data register also as timer high bit 11 2 4 Timer4 Data Register Low Bit TL4 0xE2 Bit7 Bit6 Bit5 Bit4 B...

Page 103: ...SPI interrupt enable bit 1 Enable SPI interrupts 0 Prohibited SPI Interrupt Bit6 I2CIE I2C interrupt enable bit 1 Enable I2C interrupts 0 Disable I2 C Interrupt Bit5 WDTIE WDT interrupt enable bit 1...

Page 104: ...l interrupt Bit5 PWDT WDT interrupt priority control bit 1 Set to High level Interrupt 0 Set to low level interrupt Bit4 PADC ADC interrupt priority control bit 1 Set to High level Interrupt 0 Set to...

Page 105: ...roduce an interrupt Bit5 Reserved must be 0 Bit4 ADCIF ADC interrupt flag bit 1 ADC conversion is completed and software zeroing is required 0 The ADC conversion was not completed Bit3 PWMIF PWM globa...

Page 106: ...consists of TH3 and TL3 low 5 bits TL3 high 3 bits should be ignored The block diagram of Timer3 mode 0 is shown in the following figure T34MOD 3 EIF2 0 TL3 5Bit 12 T3M 0 4 T3M 1 TH3 8Bit interrupt r...

Page 107: ...mer 3 in mode 3 sets TL3 and TH3 to two independent timers The logic of timer 3 mode 3 is shown in the following figure TL3 operates as an 8 bit timer and uses the control bits of timer 3 such as TR3...

Page 108: ...s of TH4 8 bits and TL4 low 5 bits TL4 high three bits should be ignored The block diagram of Timer4 mode 0 is shown in the following figure T34MOD 7 EIF2 1 TL4 5Bit 12 T4M 0 4 T4M 1 TH4 8Bit interrup...

Page 109: ...e below The overflow from TL4 not only makes TF4 1 but also reloads the contents of TH4 from software to TL4 The value of TH4 remains unchanged during Reloading The block diagram of Timer4 mode 2 is s...

Page 110: ...red before hibernation the LSE oscillator and LSE timer can continue to operate without being affected while the chip is asleep If the LSE timed wake function is set before sleep the system will wake...

Page 111: ...rol 1 Enable 0 Disable Bit6 LSEWUEN LSE timer wake up enable control 1 Enable 0 Disable Bit5 LSECNTEN LSE as timer count enable control 1 Enable 0 Disable Bit4 LSESTA LSE steady state bit read only 1...

Page 112: ...pt Bit2 PLSE LSE interrupt priority control bit 1 Set to High level Interrupt 0 Set to low level interrupt Bit1 Bit0 Reserved must be 0 When the count value of the LSE timer is equal to the timer valu...

Page 113: ...g bit set to 1 when the count value is equal to the timing value and update the timing value to the value in the timer data register i e the LSE timing value is the last time LSECRH 7 0 LSECRL 7 0 val...

Page 114: ...sters 13 2 1 WUTCRH Register 0xBD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 WUTCRH WUTEN WUTPS1 WUTPS0 WUTD11 WUTD10 WUTD9 WUTD8 R W R W R R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 WUTEN...

Page 115: ...for the WUT counter There are two internal wake up timer registers WUTCRH and WUTRCL Bit7 of the WUTCRH register is an internal timed wake up enable bit WUTEN 1 Turn on the timed wake up function WUT...

Page 116: ...prescale selection bit 000 Fsys 1 001 Fsys 2 010 Fsys 4 011 100 101 110 111 Fsys 8 Fsys 16 Fsys 32 Fsys 64 Fsys 128 14 2 2 The BRT Timer Data is Loaded With a Low 8 bit Register BRTDL F5C1H Bit7 Bit6...

Page 117: ...ual to FFFFH the BRT counter overflows After the overflow the initial value of the count is automatically loaded into the counter and then the count is re counted The overflow signal of the BRT counte...

Page 118: ...Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CRCIN CRCIN7 CRCIN6 CRCIN5 CRCIN4 CRCIN3 CRCIN2 CRCIN1 CRCIN0 R W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 Bit0 CRCIN 7 0 Enter the 8 b...

Page 119: ...end the data 12345678H write the value to the CRCN register in the order of 12H 34H 56H 78H read from the CRCRDL CRCDH register as CRCDL 0xF0 CRCDH 0x67 that is the result of the CRC operation in the...

Page 120: ...Bit1 Bit0 BUZCON BUSEN BUZCKS1 BUZCKS0 R W R W R R R R R R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 BUSEN BUZZER enable bit 1 Enable 0 Disable Bit6 Bit2 Reserved must be 0 Bit1 Bit0 BUZCKS 1 0 BUZZER d...

Page 121: ...e output frequency is Fbuz 8MHz 2 125 16 2KHz 2 Set Fsys 16MHz BUZCKS 1 0 11 and BUZDIV 125 The buzzer drive output frequency is Fbuz 16MHz 2 125 64 1KHz 3 Set Fsys 24MHz BUZCKS 1 0 11 and BUZDIV 94 T...

Page 122: ...a single interrupt vector entry 17 2 Characteristic The PWM module has the following features 6 independent 16 bit PWM control modes 6 independent outputs PG0 PG1 PG2 PG3 PG4 PG5 3 sets of complementa...

Page 123: ...ys Divider0 PWM Counter0 PWM Counter1 PWM Counter2 PWM Counter3 PWM Counter4 PWM Counter5 PWMnDIV PWM0 compare circuit PWM1 compare circuit PWM2 compare circuit PWM3 compare circuit PWM4 compare circu...

Page 124: ...oint PGn will output low and PWMnZIF will be set to 1 When the CNTn count reaches zero if PWMnCNTM 1 CMPn and PERIODn will be reloaded The relevant parameters for edge alignment are as follows High ti...

Page 125: ...complementary mode each set of complementary PWM pairs supports inserting a dead band delay and the inserted dead zone time is as follows PWM0 1 Dead zone PWM01DT 1 TPWM0 PWM2 3 Dead zone PWM23DT 1 T...

Page 126: ...cycle and clock divider control of PG1 PG3 PG5 are determined by the PG0 PG2 PG4 related registers respectively that is in addition to the corresponding output enable control bit PWMnOE the PG1 PG3 PG...

Page 127: ...0 controls PG2 PG4 PG1 controls PG3 PG5 0 All PWM channel signals are independent of each other Bit2 Reserved must be 0 Bit1 Reserved must be 0 Bit0 Reserved must be 0 17 5 2 PWM Output Enable Control...

Page 128: ...C F124H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM23PSC PWM23PSC7 PWM23PSC6 PWM23PSC5 PWM23PSC4 PWM23PSC3 PWM23PSC2 PWM23PSC1 PWM23PSC0 R W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0...

Page 129: ...ng Enable Control Register PWMLOADEN F129H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMLOADEN PWM5LE PWM4LE PWM3LE PWM2LE PWM1LE PWM0LE R W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 B...

Page 130: ...PWMn counter stops the software writes 0 and the counter stops and clears the counter value The brake triggers the bit hardware to clear 0 Single shot mode completes the bit hardware clearance 0 17 5...

Page 131: ...it7 Bit0 PWMDnL 7 0 PWM channel n compare data duty cycle data registers 8 bits lower 17 5 15 PWM Compare Data Register High 8 BitS PWMDnH n 0 5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMDnH PWMDnH7...

Page 132: ...Delay Data Register PWM23DT F162H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM23DT PWM23DT7 PWM23DT6 PWM23DT5 PWM23DT4 PWM23DT3 PWM23DT2 PWM23DT1 PWM23DT0 R W R W R W R W R W R W R W R W R W Reset valu...

Page 133: ...e and priority of the PWM can be set by the following relevant register bits 17 6 1 Interrupt Mask Register EIE2 0xAA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIE2 SPIIE I2CIE WDTIE ADCIE PWMIE ET4 ET3...

Page 134: ...gh level Interrupt 0 Set to low level interrupt Bit3 PPWM PWM interrupt priority control bit 1 Set to High level Interrupt 0 Set to low level interrupt Bit2 PLED LED dot matrix scan interrupt priority...

Page 135: ...it4 Bit3 Bit2 Bit1 Bit0 PWMZIF PWM5ZIF PWM4ZIF PWM3ZIF PWM2ZIF PWM1ZIF PWM0ZIF R W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 Bit6 Reserved must be 0 Bit5 Bit0 PWMnZIF PWM channe...

Page 136: ...he SEG port current is selectable in 16 steps and the maximum current can reach 40mA VOH 3 5V VDD 5V 18 3 Related Registers 18 3 1 LED Drive Mode Select Register LEDMODE F769O CLOCK Bit7 Bit6 Bit5 Bit...

Page 137: ...lock COM selection description table DUTY ICOM0 ICOM1 ICOM2 ICOM3 ICOM4 ICOM5 ICOM6 ICOM7 Effective SEG mouth 11 LED_C0 LED_C1 LED_C2 LED_C3 LED_S0 LED_S15 10 LED_C0 LED_C1 LED_C2 LED_C3 LED_C4 LED_S1...

Page 138: ...R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 Bit0 COMT 7 0 COM port effective time setting Note It is forbidden to set the 0x00 COM COMT 7 0 1 TLED_CLK 18 3 6 COM Port Enable Control Regis...

Page 139: ...8n When com0 port is active SEG 8n 7 SEG 8n port data output 1 High level 0 Low level 18 3 10 COM1 Corresponding SEG Data Register LEDC1DATAn n 0 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDC1DATAn S...

Page 140: ...H LEDC4DATA1 Address F751H Bit7 Bit0 SEG 8n 7 8n When com4 port is active SEG 8n 7 SEG 8n port data output 1 High level 0 Low level 18 3 14 COM5 Corresponding SEG Data Register LEDC5DATAn n 0 1 Bit7 B...

Page 141: ...ue 0 0 0 0 1 1 1 1 Bit7 Bit4 Reserved must be 0 Bit3 Bit0 DRC 3 0 Pull current drive selection control position control P04 P05 P06 P07 four ports 0000 0mA 1000 21 6mA 0001 2 7mA 1001 24 3mA 0010 5 4m...

Page 142: ...010 27 0mA 0011 8 1mA 1011 29 7mA 0100 10 9mA 1100 32 4mA 0101 13 5mA 1101 35 1mA 0110 16 2mA 1110 37 8mA 0111 18 9mA 1111 40 5mA 18 3 20 P20 P23 Drive Current Control Register LEDSDRP2L F714H Bit7 Bi...

Page 143: ...efault value LEDMODE 0xAA Matrix drive mode SEG6 P12 software drive P12 pin current drive enable bit 1 The pull current drive of the P12 pin is configured by the LEDSDRP1L register 0 The pull current...

Page 144: ...current drive of the P06 pin is configured by the LEDSDRP0H register 0 The pull current drive of the P06 pin is the default value Bit1 LEDENL1 LEDMODE 0xAA dot matrix drive mode LED1 P01 pin function...

Page 145: ...y the LEDSDRP2L register 0 The pull current drive of the P22 pin is the default Bit5 LEDENH5 LEDMODE 0xAA 1 Invalid 0 Invalid LEDMODE 0xAA Matrix drive mode SEG13 P21 software drive P21 pin current dr...

Page 146: ...e bit 1 The pull current drive of the P15 pins is configured by the LEDSDRP1H register 0 The pull current drive of the P15 pin is the default value Bit0 LEDENH0 LEDMODE 0xAA dot matrix drive mode LED8...

Page 147: ...value 0 0 0 0 0 0 0 0 Bit7 P0DR7 P07 drive current selection 1 150mA 0 50mA Bit6 P0DR6 P06 drive current selection 1 150mA 0 50mA Bit5 P0DR5 P05 drive current selection 1 150mA 0 50mA Bit4 P0DR4 P04...

Page 148: ...relevant configuration registers of the LED driver the corresponding LED driver output waveform can be set The LED is configured with 1 4DUTY co negative drive mode and the waveform is shown in the fo...

Page 149: ...Each lamp supports two on time options each with a 16 bit timing setting Each lamp display data is individually selectable The LED dot matrix driver supports cyclic scan mode and interrupt scan mode...

Page 150: ...l resolve the light address and the current scan address and automatically complete the output control of the corresponding IO port Can be configured 4x4 5x5 6x6 6x7 7x7 7x8 8x8 different size dot mat...

Page 151: ...23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 The 7 7 dot matrix is shown in the following figure 0 1 2 3...

Page 152: ...8 9 10 11 12 13 14 16 17 18 19 20 21 22 24 25 26 27 28 29 30 32 33 34 35 36 37 38 40 41 42 43 44 45 46 LED0 LED1 LED2 LED3 LED4 LED5 LED6 The 6 6 dot matrix is shown in the following figure 0 1 2 3 4...

Page 153: ...5 5 dot matrix is shown in the following figure 0 1 2 3 4 8 9 10 11 12 16 17 18 19 20 24 25 26 27 28 32 33 34 35 36 LED0 LED1 LED2 LED3 LED4 LED5 The 4 4 dot matrix is shown in the following figure 0...

Page 154: ...nterface control timing is shown in the following figure 0 1 2 8 9 10 LED0 LED1 LED2 Schematic diagram of two lights 1 2 3 4 5 6 7 8 9 10 11 12 1 0 0 1 1 0 016 4 096ms LED light 0 Scan procedure LED l...

Page 155: ...er values Invalid 19 4 2 LED Dot Matrix Drive Controller LEDCON1 F765H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDCON1 SCAN_START DUTY2 DUTY1 DUTY0 SCAN_MODE CLKSEL1 CLKSEL0 R W R W R W R W R W R W R...

Page 156: ...FLED CLK 15 0 1 19 4 5 LED Dot Matrix Drive First Stage Configuration Register Higher 8 Bits scan1WH F761H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCAN1WH SCAN1WH7 SCAN1WH6 SCAN1WH5 SCAN1WH4 SCAN1WH3...

Page 157: ...DnDATA6 LEDnDATA5 LEDnDATA4 LEDnDATA3 LEDnDATA2 LEDnDATA1 LEDnDATA0 R W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 LED0DATA Address F740H LED1DATA Address F741H LED2DATA Address F744H...

Page 158: ...lay cycle configuration Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LED0SEL0 Led7 Led6 Led5 Led4 Led3 Led2 Led1 Led0 LED1SEL1 Led15 Led14 Led13 Led12 Led11 Land10 Led9 Led8 LED2SEL2 Led23 Led22 Led21 Led2...

Page 159: ...function of the LED7 pins is Disabled as a GPIO function The current drive of the LED7 pin is the default LEDMODE 0xAA Matrix drive mode SEG7 P13 software drive P13 pin current drive enable bit 1 The...

Page 160: ...0xAA Matrix drive mode SEG3 P07 software drive P07 pin current drive enable bit 1 The pull current drive of the P07 pin is configured by the LEDSDRP0H register 0 The pull current drive of the P07 pin...

Page 161: ...AA Matrix drive mode SEG15 P23 software drive P23 pin current drive enable bit 1 The pull current drive of the P23 pin is configured by the LEDSDRP2L register 0 The pull current drive of the P23 pin i...

Page 162: ...s the default value Bit1 LEDENH1 LEDMODE 0xAA 1 Invalid 0 Invalid LEDMODE 0xAA Matrix drive mode SEG9 P15 software drive P15 pin current drive enable bit 1 The pull current drive of the P15 pins is co...

Page 163: ...W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 PSPI SPI interrupt priority control bit 1 Set to High level Interrupt 0 Set to low level interrupt Bit6 PI2C I2C interrupt priority...

Page 164: ...clock polarity and phase The system can be configured as a master device or slave device and when the SPI is configured as a host device the software chooses one of eight different bit rates for the...

Page 165: ...Select P01 for the MOSI channel for the SPI PS_MISO 0x02 Select P02 as the MISO channel for the SPI PS_NSS 0x03 Select P03 as the NSS channel for the SPI P00CFG 0x03 P00 multiplexing for SCLK functio...

Page 166: ...data cannot be written to the shifter until the previous data transfer is complete However the received data is transmitted to a parallel read data buffer so the shifter is free to receive a second se...

Page 167: ...SPI is configured as a slave device the SI pin is the slave device input data line and the SO is the slave device output data line When the SPI is configured as a host device the MI pin is the host d...

Page 168: ...is low when idle Bit2 CPHA SPI clock phase select bit Bit1 Bit0 SPR 1 0 SPI Clock Frequency Select Bit 1 0 For details of frequency control see the table below The SPR2 SPR0 controls the SPI clock div...

Page 169: ...bit read only 1 SPI transmission is completed read SPSR first then read write SPDR and then clear zero 0 The SPI was not transmitted Bit6 WCOL SPI write violation interrupt flag bit read only 1 When...

Page 170: ...software control Place SSCEN in host mode when SSCEN is set to 1 the NSS line outputs the contents of the SSCR register while the transmission is in progress and the NSS is high when the transmission...

Page 171: ...onflicts are during the data transmission process when the NSS is low the first data starts to be sent from the moment to the 8th SCLK falling edge if you write SPDR during this period a write conflic...

Page 172: ...When an SPDR register write operation is performed while an SPI transfer is in progress a write violation error occurs In slave mode when CPHA is cleared a write collision error may occur as long as t...

Page 173: ...d NSS does not immediately become low When the NSS is low you need to wait for the second edge of the SCLK to start before entering the real data transfer state Between writing the SPDR and starting t...

Page 174: ...are not selected do not interfere with SPI bus activity On the SPI host device the slave selection line may be selectively used to indicate multi master bus competition 20 7 3 CPHA 0 Transfer Format T...

Page 175: ...he master and slave this diagram can be interpreted as a master or slave timing diagram The MISO signal is output from the Slave and the MOSI signal is the host output The slave selection input of the...

Page 176: ...ly completed but depending on the configuration of the SPI system there may be other tasks Since the SPI bit rate does not affect the timing of the end period only the fastest rate is considered in th...

Page 177: ...ising edge of the SCLK clock The master mode timing diagram is shown in the following figure D7 D6 D5 D4 D3 D2 D1 D0 MOSI NSS 1 CLK 1 CLK SCLK 20 9 2 Slave Mode Transmission When the clock polarity of...

Page 178: ...1 the SPIIF in the SPI master mode generates clKs after the rising edge of the eighth SCLK clock in each frame of data and the timing diagram is shown in the following figure MOSI SPIIF 2 CLK SCLK D7...

Page 179: ...l Interrupt 0 Set to low level interrupt Bit5 PWDT WDT interrupt priority control bit 1 Set to High level Interrupt 0 Set to low level interrupt Bit4 PADC ADC interrupt priority control bit 1 Set to H...

Page 180: ...produce an interrupt Bit5 Reserved must be 0 Bit4 ADCIF ADC interrupt flag bit 1 ADC conversion is completed and software zeroing is required 0 The ADC conversion was not completed Bit3 PWMIF PWM glob...

Page 181: ...Support 4 working modes master transmission master reception slave transmission slave reception Supports 2 transfer speed modes Standard up to 100Kb s Fast up to 400Kb s Perform arbitration and clock...

Page 182: ...register I2CMSR 0xF5 The master transmits the data register I2CMBUF The master receives data register I2CMBUF 0xF6 Timing cycle register I2CMTP Timing cycle register I2CMTP 0xF7 The master mode contro...

Page 183: ...cause the I2C Bus controller to automatically send a reply after each byte When the I2C bus controller no longer needs to send data from the slave the bit must clear 0 Master mode control registers 0x...

Page 184: ...at the START condition followed by the response TOCAIVE operation Master remains in receiver mode 1 0 1 1 1 Repeat THEART followed by the SEND and STOP conditions 1 1 0 1 1 Repeat the START condition...

Page 185: ...de 1 The I2C bus is busy and cannot be transmitted cleared by the start bit set to 1 on the bus stop condition 0 Bit5 IDLE I2C Master mode idle flag bit 1 is idle 0 is the working status Bit4 ARB_LOST...

Page 186: ...Master mode slave address Bit0 R S I2C Master mode after sending slave address after receiving sending status selection bits 1 Receive data after correct addressing 0 The data is sent after correct ad...

Page 187: ...Theown address of the I2C slave mode 21 4 2 I2C Slave Mode Control and Status Registers I2CSCR I2CSSR Slave mode control registers and slave mode status registers occupy a register address using diffe...

Page 188: ...stop condition is generated Slave mode status register I2CSSR 0xF2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 I2CSSR SENDFIN TREQ RREQ R W R R R Reset value 0 0 0 0 0 0 0 0 Bit7 Bit3 Reserved must be 0...

Page 189: ...2CIF will be set to 1 I2CIF automatically clears 0 only if all four flag bits are 0 21 5 1 Interrupt Mask Register EIE2 0xAA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIE2 SPIIE I2CIE WDTIE ADCIE PWMIE...

Page 190: ...l interrupt Bit5 PWDT WDT interrupt priority control bit 1 Set to High level Interrupt 0 Set to low level interrupt Bit4 PADC ADC interrupt priority control bit 1 Set to High level Interrupt 0 Set to...

Page 191: ...oduce an interrupt Bit5 Reserved must be 0 Bit4 ADCIF ADC interrupt flag bit 1 ADC conversion is completed and software zeroing is required 0 The ADC conversion was not completed Bit3 PWMIF PWM global...

Page 192: ...address 0x39 00111001 21 6 1 Single Receive The following figure shows the sequence of signals received by I2C during a single data session Single receive sequence Starting conditions The I2C is addr...

Page 193: ...he sequence of signals sent by I2C during a single data session Single send sequence Starting conditions I2C is addressed by the I2C master as a transmitter The address is confirmed by I2C Datais tran...

Page 194: ...ed by I2C during continuous data reception Continuous receive sequence Start conditions I2C is addressed by the I2C master as a receiver The address is confirmed by I2C 1 Data is received by I2C 2 The...

Page 195: ...nsecutive send sequences Send conditions I2C is addressed by the I2C master as a transmitter The address is confirmed by I2C 1 The data is sent by I2C 2 Data I2C master acknowledges data 3 The last da...

Page 196: ...data bytes in that bit 9 in the address byte is 1 and data bytes are 0 At SMn2 1 the slave is not interrupted by bytes of data The address byte will interrupt all slaves The addressed slave will clea...

Page 197: ...4 001 Select Timer4 as the baud rate generator for UART1 FUNCCR 6 4 010 Timer2 was selected as the baud rate generator for UART1 FUNCCR 6 4 011 BRT was chosen as the baud rate generator for UART1 22...

Page 198: ...rate information of the UART clock source 1 SMODn 0 T1M 1 T4M 1 baud rate Fsys 8MHz Fsys 16MHz Fsys 24MHz Fsys 48MHz Kbps TH1 TH4 Current Rate Error TH1 TH4 Current Rate Error TH1 TH4 Current Rate Err...

Page 199: ...5516 37500 2 34 65497 38462 0 16 115200 65523 115385 0 16 250000 65530 250000 0 500000 65533 500000 0 4 SMODn 1 BRTCKDIV 0 baud rate Fsys 8MHz Fsys 16MHz Fsys 24MHz Fsys 48MHz Kbps BRTH BRTL Current R...

Page 200: ...RT1_CKS2 UART1_CKS1 UART1_CKS0 UART0_CKS2 UART0_CKS1 UART0_CKS0 R W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Registers in BANK0 Bit7 Reserved must be 0 Bit6 Bit4 UART1_CKS 2 0 Timer...

Page 201: ...ts 1 Enable 0 Disable Bit3 UnTB8 The 9th bit of sending data mainly used for sending in 9 bit asynchronous mode 1 The 9th digit is 1 0 The 9th digit is 0 Bit2 UnRB8 The 9th bit of receiving data mainl...

Page 202: ...T1 baud rate 0 The UART1 baud rate is normal Bit5 Bit3 Reserved must be 0 Bit2 THEIR STOP status function wake up enable bit The system can be restarted by a power down reset or an enabled external re...

Page 203: ...EX0 R W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 SHE Global interrupt enable bits 1 Enable all unblocked interrupts 0 Disable all interrupts Bit6 ES1 UART1 interrupt enable bi...

Page 204: ...it 1 Set to High level Interrupt 0 Set to low level interrupt Bit4 PS0 UART0 interrupt priority control bit 1 Set to High level Interrupt 0 Set to low level interrupt Bit3 PT1 TIMER1 interrupt priorit...

Page 205: ...s shown in the following figure D0 D1 D2 D3 D4 D5 D6 D7 RXDn TIn TXDn 22 6 2 Mode 1 8 Bit Asynchronous Mode Variable Baud Rate The pin RXDn is used as the input and the TXDn is used as the serial outp...

Page 206: ...ace at send time bit TBn8 in SCONn acts as the 9th bit output and on receive bit 9 affects RBn8 in SCONn The Mode 3 timing diagram is shown in the following figure D1 D2 D3 D4 D5 D6 TXDn TIn RXDn TB8...

Page 207: ...bit binary result and saves the result in the ADC result register ADRESL and ADRSH and the ADC can generate an interrupt after the conversion is complete The ADC conversion results are compared to th...

Page 208: ...an analog port Note Applying an analog voltage to a pin defined as a digital input may cause an overcurrent in the input buffer 23 2 2 Channel Selection The register ADCCHS bit determines which channe...

Page 209: ...The appropriate TAD specification must be met to obtain the correct conversion results and the following table is an example of the correct selection of an ADC clock Fsys TAD 8MHz Fsys 8 16MHz Fsys 1...

Page 210: ...1 to the ADGO bit when the ADC is idle 23 3 1 The External Port Edge Triggers the ADC The ADET pin edge automatically triggers the ADC conversion At this point ADTGS 1 0 needs to be 11 select externa...

Page 211: ...will Zero ADGO bit Place the ADCIF flag at bit set to 1 Update the ADRESH ADRESL register with the new result of the conversion 23 5 3 Terminate the Conversion If the conversion must be terminated bef...

Page 212: ...t the ADC interrupt flag bit this is required if interrupts are Enabled Note If the user attempts to resume sequential code execution after waking the device from sleep mode the global interrupt must...

Page 213: ...n result format select bits 1 Right alignment 0 Left aligned Bit5 Bit2 ANACH 3 0 ADC channel 63 input source select bit 0000 BGR 1 2V 0001 Reserved prohibited use 0010 Reserved prohibited use 0011 Res...

Page 214: ...ys 8 110 Fsys 128 011 Fsys 16 111 Fsys 256 Bit3 Bit0 Reserved must be 0 23 6 3 AD Control Register ADCON2 0xE9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCON2 ADCEX ADTGS1 ADTGS0 ADEGS1 ADEGS0 R W R W...

Page 215: ...rohibited access 000100 AIN4 010100 Prohibited access 100100 Prohibited access 000101 AIN5 010101 Prohibited access 100101 Prohibited access 000110 AIN6 010110 Prohibited access 100110 Prohibited acce...

Page 216: ...ardware Trigger Delay Data Register ADDLYL 0xD3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADDLYL ADDLY7 ADDLY6 ADDLY5 ADDLY4 ADDLY3 ADDLY2 ADDLY1 ADDLY0 R W R W R W R W R W R W R W R W R W Reset value 0...

Page 217: ...ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 R W R R R R R R R R Reset value X X X X X X X X Bit7 Bit0 ADDRESS 7 0 ADC result register bit 12 bits converted to bits 7 0 of the result 23 6 11 AD Comparator Data...

Page 218: ...R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 LDOEN ADC_LDO enabled 1 LDO enable the reference voltage can only select the voltage corresponding to VSEL 1 0 0 LDO prohibits the refe...

Page 219: ...t6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIE2 SPIIE I2CIE WDTIE ADCIE PWMIE ET4 ET3 R W R W R W R W R W R W R W R W R W Reset value 0 0 0 0 0 0 0 0 Bit7 SPIIE SPI interrupt enable bit 1 Enable SPI interrupts...

Page 220: ...l interrupt Bit5 PWDT WDT interrupt priority control bit 1 Set to High level Interrupt 0 Set to low level interrupt Bit4 PADC ADC interrupt priority control bit 1 Set to High level Interrupt 0 Set to...

Page 221: ...roduce an interrupt Bit5 Reserved must be 0 Bit4 ADCIF ADC interrupt flag bit 1 ADC conversion is completed and software zeroing is required 0 The ADC conversion was not completed Bit3 PWMIF PWM globa...

Page 222: ...d separately into a separate ground and then a point should be connected to the common ground of the whole machine Avoid high voltage high current high frequency operation of the motherboard and touch...

Page 223: ...L MADRH registers hold the address of the accessed MDATA unit or the address of CRC checksum PCRCDL PCRCDH registers are used to maintain the running results of the program CRC and MCTRL registers are...

Page 224: ...TA 0xFE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MDATA MDATA7 MDATA6 MDATA5 MDATA4 MDATA3 MDATA2 MDATA1 MDATA0 R W R W R W R W R W R W R W R W R W Reset value X X X X X X X X Bit7 Bit0 MDATA 7 0 Data t...

Page 225: ...n Bit5 TAKE Operation error flag bit write 0 cleared 1 Before the programming operation begins the data in the detection programming address is not FFH not erased and the write operation terminates im...

Page 226: ...s MADRL MADRH and the results are saved in the register PCRCDL PCRCDH This CRC operation can only access the program storage space and the data storage space cannot be accessed During the program spac...

Page 227: ...228 239 Rev 1 00 CMS80F731x Reference Manual 6 Read the program CRC check result PCRCDL stores the lower 8 bits CRC operation result of the program PCRCDH stores the higher 8 bits CRC operation result...

Page 228: ...R R R R R R R R Reset value X X X X X X X X Bit7 Bit0 UID 7 0 UID1 F5E1H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID1 UID15 UID14 UID13 UID12 UID11 UID10 UID9 UID8 R W R R R R R R R R Reset value X X...

Page 229: ...t value X X X X X X X X Bit7 Bit0 UID 47 40 UID6 F5E6H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID6 UID55 UID54 UID53 UID52 UID51 UID50 UID49 UID48 R W R R R R R R R R Reset value X X X X X X X X Bit7...

Page 230: ...ue X X X X X X X X Bit7 Bit0 UID 79 72 UID10 0xF5EA F5EAH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID10 UID87 UID86 UID85 UID84 UID83 UID82 UID81 UID80 R W R R R R R R R R Reset value X X X X X X X X...

Page 231: ...default The FLASH data area is encrypted and the value read out by the flashing emulator after encryption is 00H 4 LVR Low Voltage Reset 1 8V default 2 0V 2 5V 3 5V 5 DEBUG debug mode DISABLE default...

Page 232: ...port is turned on 11 WAKE UP_WAIT TIME sleep wake up waits for oscillator to stabilize by default to 1 0s 50us 5ms 100us 10ms 500us 500ms 1ms 1 0s default 12 CPU_WAITCLOCK memory wait clock selection...

Page 233: ...e chip A typical online serial programming connection method is shown in the following figure R1 R2 VDD GND DSDA DSCK VDD GND DAT CLK Emulator burner signal To normal connection such as connecting VDD...

Page 234: ...s When the debug state enters sleep mode idle mode the system power supply and oscillator do not stop working and the sleep wake function can be simulated in this state If you need to focus on power c...

Page 235: ...scription Symbol Description Rn Working registers R0 R 7 Direct The cell address 00H FFH of the internal data memory RAM or the address in the special function register SFR Ri Indirection register R0...

Page 236: ...1 DEC Rn Register minus 1 DEC direct Direct addressing unit minus 1 DEC Ri Indirect addressed RAM minus 1 MANDL A B Accumulator multiplier by register B DIV A B The accumulator is divided by register...

Page 237: ...take Immediately send indirect addressed RAM MOV DPTR data16 The 16 bit immediate number sends a data pointer MOVC A A DPTR Lookup table data feed accumulator DPTR as base address MOVC A A PC Lookup t...

Page 238: ...A dandrec t r the Accumulators are transferred unequally from direct addressing units CJNE A data r the Accumulator with immediate number unequal transfer CJNE Rn data r el Registers are transferred...

Page 239: ...www mcu com cn 240 239 Rev 1 00 CMS80F731x Reference Manual 30 Version Revision Notes The version number Time Revision content V1 00 September 2020 Initial release...

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