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CMS80F731x Reference Manual
23.2.4
Convert the Clock
The converted clock source can be selected by software setting the ADCKS bit of the ADCON1 register. The following 8
possible clock frequencies are available:
◆
F
sys
/2
◆
F
sys
/4
◆
F
sys
/8
◆
F
sys
/16
◆
F
sys
/32
◆
F
sys
/64
◆
F
sys
/128
◆
F
sys
/256
The time to complete a bit conversion is defined as T
AD
. A full 12-bit conversion takes 18.5 T
AD
cycles (the time it takes to
complete a conversion ADGO lasts high). The appropriate T
AD
specification must be met
to obtain the correct conversion results,
and the following table is an example of the correct selection of an ADC clock.
Fsys
T
AD
8MHz
F
sys
/8
16MHz
F
sys
/16
32MHz
F
sys
/32
48MHz
F
sys
/64
Note: Any change in the system clock frequency will change the frequency of the ADC clock, which can negatively affect the
ADC conversion results.
23.2.5
Result Format
The results of the 12-bit A/D conversion can be in two formats: left-aligned or right-aligned. The output format is controlled
by the ADFM bit of the ADCON0 register.
When ADFM=0, the AD conversion result is left-aligned;
When ADFM=1, the AD conversion result is right-aligned.
