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CMS80F731x Reference Manual
6.4.4
The Clear Operation For the Interrupt Flag Bit
The clear operation of the interrupt flag is divided into the following categories:
◆
Automatic hardware cleanup (requires entry into interrupt service)
◆
Software cleanup
◆
Read/write operations are cleared
1)
The hardware automatically clears the flag bits
The bits that support hardware auto-clearing are the interrupt flag bits generated by IN0, INT1, T0, T1, T3, and T4. The
condition for the hardware to automatically clear the flag is: open the global interrupt enable bit EA=1, and open the
corresponding interrupt enable bit, after the interrupt is generated, the system enters the corresponding interrupt service program,
and the flag bit is automatically cleared. If interrupt enables shutdown, these flags can also be cleared using software.
2)
The flag bits that the software clears
There are flags in the system that can only be cleared with software. These flags are not automatically cleared after entering
the interrupt service program and require the software to write 0 to clear. Otherwise, after exiting the interrupt service program,
you will enter the interrupt service program again.
3)
The flag bit cleared by the R/W operations
The flag bit in the system is not written to zero to the flag bit, but requires reading/writing other registers to clear the flag bit.
For example, if the transmission completion flag bit SPISIF in the SPI interrupt flag register is set to 1, you need to read spsr
first, and then read/write SPDR and then clear zero.
Software cleanup operations require attention: when multiple interrupt flags are in the same register, and the moments
these flags are generated are not related to each other, it is not recommended to use read-modify-write operations. For
example, the PWMUIF interrupt flag register, which contains the upward comparison interrupt of the PG0-PG5 channel, these
interrupt flag bits are not related to each other. When PG0 produces an up-to-compare interrupt, the value of PWMUIF is
0x01, and a read-modify-write operation clears the bit after entering the interrupt service program
PWMUIF &= 0xFE;
This operation is implemented by reading the value of PWMUIF back to the CPU, then performing the operation, and
finally sending it back to PWMUIF. If the interrupt flag bit PWMUIF[1] of PG1 is set to 1 after the CPU read, and PWMUIF[1] is
0 when read, the operation is performed and sent back to PWMUIF[1] is also 0, at which point the upward interrupt flag bit
PWMUIF[1] that PG1 has generated will be cleared.
Clear the interrupt flag bits of the above type, it is recommended to write 0 directly, other unrelated flag bits to write 1:
PWMUIF = 0xFE. This operation has no practical effect on unrelated interrupt flag write 1.
