Cmsemicon CMS80F731 Series, Reference Manual

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CMS80F731x Reference Manual
20.10 SPI Interrupt
The interrupt number of the SPI is 22, where the interrupt vector is 0x00B3. To enable an SPI interrupt, it must set its enable
bit SPIIE to 1 and the global interrupt enable bit EA to 1.
If the SPI-related interrupt enables are all turned on, the CPU will enter the interrupt service program when the SPI global
interrupt indicator bit SPIIF=1. The SPIIF operation properties are read-only and independent of the state of SPIIE.
After the SPI status register SPSR has either of the transmission completion flagSISIF and the write violation WCOL flag 1,
the SPI global interrupt indicator bit SPIIF will be set to 1. SPIIF automatically clears 0 only if all three flag bits are 0.
When the clock polarity of the SPI is CPOL=0 and the clock phase is CPHA=1, the SPIIF in the SPI master mode
generates clKs after the rising edge of the eighth SCLK clock in each frame of data, and the timing diagram is shown in the
following figure:
MOSI
SPIIF
2 CLK
SCLK
D7 D6
D5 D4 D3 D2 D1 D0
20.10.1
Interrupt Mask Register EIE2
0xAA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EIE2 SPIIE I2CIE WDTIE ADCIE PWMIE -- ET4 ET3
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7 SPIIE: SPI interrupt enable bit;
1= Enable SPI interrupts;
0= Disable SPI Interrupt.
Bit6 I2CIE: I2C interrupt enable bit;
1= Enable I2C interrupts;
0= Forbidden I
2
C Interrupt.
Bit5 WDTIE: WDT interrupt enable bit;
1= Enable WDT overflow interrupts;
0= Disable WDT overflow interrupts.
Bit4 ADCIE ADC interrupt enable bit;
1= Enable ADC interrupts;
0= Disable ADC interrupts.
Bit3 PWMIE: PWM global interrupt enable bit;
1= Enable all PWM interrupts;
0= Disable all PWM interrupts.
Bit2 -- Reserved, must be 0.
Bit1 ET4: Timer4 interrupt enable bit;
1= Enable Timer4 interrupts;
0= Forbidden Timer4 Interrupt.
Bit0 ET3: Timer3 interrupt enable bit;