Cmsemicon CMS80F731 Series, Reference Manual

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CMS80F731x Reference Manual
10.2.3
Timer2 Data Register High TH2
0xCD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TH2
TH27 TH26 TH25 TH24 TH23 TH22 TH21 TH20
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit0 TH2<7:0>: Timer 2 high-bit data register (also as counter low).
10.2.4
Timer2 Compare/Capture/Auto Reload Register Low Bit RLDL
0xCA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RLDL
RLDL7 RLDL6 RLDL5 RLDL4 RLDL3 RLDL2 RLDL1 RLDL0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit0 RLDL<7:0>: Timer 2 compare/capture/auto reload register low.
10.2.5
Timer2 Compare/Capture/Auto Reload Register High Bit RLDH
0xCB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RLDH
RLDH7 RLDH6 RLDH5 RLDH4 RLDH3 RLDH2 RLDH1 RLDH0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit0 RLDH<7:0>: Timer 2 compare/capture/auto reload register high bits.
10.2.6
Timer2 Compares/Captures Channel 1 Register Low Bit CCL1
0xC2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CCL1
CCL17 CCL16 CCL15 CCL14 CCL13 CCL12 CCL11 CCL10
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit0 CCL1<7:0>: Timer 2 compares/captures channel 1 register low.
10.2.7
Timer2 Compares/Captures Channel 1 Register High Bit CCH1
0xC3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CCH1
CCH17 CCH16 CCH15 CCH14 CCH13 CCH12 CCH11 CCH10
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset value 0 0 0 0 0 0 0 0
Bit7~Bit0 CCH1<7:0>: Timer 2 compares/captures channel 1 register high bits.