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CET Electric Technology
Figure 4-24 FREQ L Alarm Logic Diagram
4.3.8 Unbalance Alarm
The following table illustrates the Unbalance Alarm parameters.
Parameters
Description
Range
Default Value
I Unb. Alarm Enable
Bit 0 = Current-I, Bit 1 = Current-II
Bits 2 - 15 = Reserved
0 = Disabled
1 = Enabled
0
I Unb. H Alarm Threshold (%)
Current Unb. H Alarm Threshold
0 to 100%
0
I Unb. H Alarm Time Delay (s)
Current Unb. H Alarm Time Delay
0 to 9999 (s)
0
U Unb. Alarm Enable
Bit 0 = Voltage-I, Bit 1 = Voltage-II
Bits 2 - 15 = Reserved
0 = Disabled
1 = Enabled
0
U Unb. H Alarm Threshold (%)
Voltage Unb. H Alarm Threshold
0 to 100%
0
U Unb. H Alarm Time Delay (s)
Voltage Unb. H Alarm Time Delay
0 to 9999 (s)
0
Table 4-15 Unbalance Alarm Parameters
The U/I Unb. Alarm Return Limits are illustrated below:
U/I Unb. Alarm Return Limit = U/I Unb. Alarm Limit x (1 – Universal Hysteresis)
The logic diagram of Unbalance Alarm is illustrated in Figure 4-25.
Figure 4-25 Unbalance Alarm Logic Diagram
4.3.9 Harmonic Distortion Alarm
The following table illustrates the Harmonic Distortion Alarm parameters.
Parameters
Description
Range
Default Value
Harmonic Alarm Enable
Bit 0 = Current-I, Bit 1 = Current-II
Bit 2 = Voltage-I, Bit 3 = Voltage-II
Bits 4 - 15 = Reserved
0 = Disabled
1 = Enabled
0
THD H Alarm Threshold (%)
THD H Alarm Threshold
0 to 100%
0
THD H Alarm Time Delay (s)
THD H Alarm Time Delay
0 to 9999 (s)
0
TOHD H Alarm Threshold (%)
TOHD H Alarm Threshold
0 to 100%
0
TOHD H Alarm Time Delay (s)
TOHD H Alarm Time Delay
0 to 9999 (s)
0
TEHD H Alarm Threshold (%)
TEHD H Alarm Threshold
0 to 100%
0
TEHD H Alarm Time Delay (s)
TEHD H Alarm Time Delay
0 to 9999 (s)
0
Table 4-16 Harmonic Distortion Alarm Parameters
The THD/TOHD/TEHD Alarm Return Limits are illustrated below:
THD/TOHD/TEHD Alarm Return Limit = THD/TOHD/TEHD Alarm Limit x (1 – Universal Hysteresis)
The logic diagram of Harmonic Distortion Alarm is illustrated in Figure 4-26.