
141
CET Electric Technology
2 = DI4 Closed Trigger
6504
RW
DI4~ Alarm Time Delay
13
UINT16
0* to 9999 (s)
# Available in Firmware V1.00.05 or later. ~ Available in Firmware V1.00.08 or later. ^ Available in Firmware V1.00.10 or later
Table 5-61 Alarm Setup Parameters
Notes:
1)
The calculation method
Universal Hysteresis
is listed below:
100%
Threshold
Alarm
Threshold
Return
Alarm
-
Threshold
Alarm
Hysteresis
Universal
2)
Current Alarm ON value = Breaker Rating x
Current Alarm ON Threshold
3)
The following table illustrates the details of the
Current Alarm Enable
register with a bit value of 1 meaning enabled and
0 meaning disabled.
Bits 3 - 15
Bit 2
Bit 1
Bit 0
Current Alarm Enable
Reserved
Branch Current
Mains-II Current
Mains-I Current
Table 5-62 Current Alarm Enabled Register (Reg. # 6403)
4)
The following table illustrates the details of the
ULN Alarm Enable
register with a bit value of 1 meaning enabled and 0
meaning disabled.
Bits 2 - 15
Bit 1
Bit 0
ULN Alarm Enable
Reserved
Mains-II ULN
Mains-I ULN
Table 5-63 ULN Alarm Enabled Register (Reg. # 6412)
5)
The following table illustrates the details of the
ULL Alarm Enable
register with a bit value of 1 meaning enabled and 0
meaning disabled.
Bits 2 - 15
Bit 1
Bit 0
ULL Alarm Enable
Reserved
Mains-II ULL
Mains-I ULL
Table 5-64 ULL Alarm Enabled Register (Reg. # 6417)
6)
The following table illustrates the details of the
Power/PF/I Demand and Power Demand Alarm Enable
register with a bit
value of 1 meaning enabled and 0 meaning disabled.
Bits 2 - 15
Bit 1
Bit 0
Power/PF/I Demand/Power Demand Alarm Enable
Reserved
Mains-II
Mains-I
Table 5-65 Power/PF/I Demand and Power Demand Alarm Enabled
7)
kW H Alarm Threshold is a percentage of the 3-Ø Power rating. If the H Alarm Threshold is 10%, the rated voltage is 220V
and the Breaker Rating is 100A, then the kW H Alarm setting = 220 * 100 * 3 * 10% = 6600W = 6.6kW
8)
The following table illustrates the details of the
U/I Unbalance Alarm Enable
register with a bit value of 1 meaning enabled
and 0 meaning disabled.
Bits 2 - 15
Bit 1
Bit 0
U/I Unbalance Alarm Enable
Reserved
Mains-II U/I Unbalance
Mains-I U/I Unbalance
Table 5-66 U/I Unbalance Alarm Enabled
9)
The following table illustrates the details of the
Harmonic Distortion Alarm Enable
register with a bit value of 1 meaning
enabled and 0 meaning disabled.
Bits 4 - 15
Bit 3
Bit 2
Bit 1
Bit 0
THD/TOHD/TEHD Alarm Enable
Reserved
Mains-II U
Mains-II I
Mains-I U
Mains-I I
Table 5-67 Harmonic Distortion Alarm Enabled (Reg. # 6480)
10)
The following table illustrates the details of the
Dip/Swell Alarm Enable
register with a bit value of 1 meaning enabled and
0 meaning disabled.
Bits 2 - 15
Bit 1
Bit 0
Dips/Swells Alarm Enable
Reserved
Mains-II Voltage Dip/Swell
Mains-I Voltage Dip/Swell
Table 5-68 Dips/Swells Alarm Enabled (Reg. # 6491)
11)
The following table illustrates the details of the
Phase Reversal Enable
register with a bit value of 1 meaning enabled and
0 meaning disabled.
Bits 4 - 15
Bit 3
Bit 2
Bit 1
Bit 0
Phase Reversal Alarm Enable
Reserved
Mains-II U
Mains-II I
Mains-I U
Mains-I I
Table 5-69 Phase Reversal Alarm Enabled (Reg. # 6498)