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SIMD Mode and Sequencing
3-36
ADSP-2126x SHARC Processor Hardware Reference
Reading From LCNTR in a LOOP
If a program reads
LCNTR
during the last two instructions of a terminating
loop, the value of
LCNTR
is the last
CURLCNTR
value for the loop. For
example:
R12=0x8;
LCNTR = R12, do (PC,7) until lce;
nop;
nop;
nop;
nop;
nop;
dm(I0,M0) = LCNTR;
dm(I0,M0) = LCNTR;
---------------------------------------
LCNTR is 8 in first 7 iterations, in the last iteration it is 1.
SIMD Mode and Sequencing
The DSP supports a SIMD (Single-Instruction, Multiple-Data) mode. In
this mode, both of the DSP’s processing elements (PEx and PEy) execute
instructions and generate status conditions. For more information on
SIMD computations, see
“SIMD (Computational) Operations” on
.
Because the two processing elements can generate different outcomes, the
sequencers must evaluate conditions from both elements (in SIMD mode)
for conditional (
IF
) instructions and loop (
DO
/
UNTIL
) terminations. The
DSP records status for the PEx element in the
ASTATx
and
STKYx
registers.
The DSP records status for the PEy element in the
ASTATy
and
STKYy
reg-
isters.
lists the bits in
ASTATx
and
ASTATy
, and
lists the bits in
STKYx
and
STKYy
.
Even though the DSP has dual processing elements, the sequencer does
not have dual sets of stacks. The sequencer has one PC stack, one loop
address stack, and one loop counter stack. The status bits for stacks are in
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...