ADSP-2126x SHARC Processor Hardware Reference
9-31
Serial Ports
Each of the four Multichannel Enable and Compand Select registers are
32 bits in length. These registers provide channel selection for 128 (32
bits x 4 channels = 128) channels. Setting a bit enables that channel so
that the serial port selects its word from the multiple-word block of data
(for either receive or transmit). For example, setting bit 0 in
MT0CS0
or
MT2CS0
selects word 0, setting bit 12 selects word 12, and so on. Setting bit
0 in
MT0CS1
or
MT2CS1
selects word 32, setting bit 12 selects word 44, and
so on.
Setting a particular bit to 1 in the
MT0CS
(
0–3
),
MT2CS
(
0–3
) or
MT4CS
(
0–3
)
register causes SPORT0, 2, or 4 to transmit the word in that channel’s
position of the data stream. Clearing the bit in the register causes
SPORT0’s
SPORT0_DA/B
, SPORT2’s
SPORT2_DA/B
or SPORT4’s
SPORT4_DA
data transmit signal to three-state during the time slot of that
channel.
Setting a particular bit to 1 in the
MR1CS(0-3)
,
MR3CS(0-3)
or
MR5CS(0-3)
register causes the serial port to receive the word in that channel’s position
of the data stream. The received word is loaded into the receive buffer.
Clearing the bit in the register causes the serial port to ignore the data.
Companding may be selected on a per-channel basis. Setting a bit to 1 in
any of the multichannel registers specifies that the data be companded for
that channel. A-law or
-law companding can be selected using the
DTYPE
bit in the
SPCTLx
control registers. SPORT1, 3, and 5 expand selected
MR1CCS(0–3)
MR3CCS(0–3)
MR5CCS(0–3)
Multichannel Receive Compand Select
specifies which active receive
channels (out of 128 channels) are companded.
MT0CCS(0–3)
MT2CCS(0–3)
MT4CCS(0–3)
Multichannel Transmit Compand Select
specifies which active transmit
channels (out of 128 channels) are companded.
Table 9-2. Multichannel Selection Registers (Cont’d)
Register Names
Function
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...