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ADSP-2126x SHARC Processor Hardware Reference
3-25
Program Sequencer
• TCB loading takes 16 core clock cycles to configure 4 IOP regis-
ters. This access is not divisible.
Loops and Sequencing
Another type of nonsequential program flow that the sequencer supports
is looping. A loop occurs when a
DO
/
UNTIL
instruction causes the DSP to
repeat a sequence of instructions until a condition tests true. Unlike other
processors, the SHARC automatically evaluates the loop termination con-
dition and modifies the Program Counter (
PC
) register appropriately. This
allows zero overhead looping.
In addition to the standard status flags available to all conditional instruc-
tions (
EQ
,
GT
,
LT
, and so on), a special condition instruction Loop Counter
Expired (
LCE
), is specifically used for terminating loops. This instruction
tests whether the loop has completed the required number of iterations in
the
LCNTR
register. Loops that terminate with conditions other than
LCE
have some additional restrictions. For more information, see
and
“Restrictions on Short Loops” on
. For more information on condition types in
DO
/
UNTIL
instruc-
tions, see
“Interrupts and Sequencing” on page 3-48
.
The DSP’s SIMD mode influences the execution of loops.
The
DO
/
UNTIL
instruction uses the sequencer’s loop and condition features,
as shown in
. These features provide efficient hard-
ware loops without the overhead of additional instructions to branch, test
a condition, or decrement a counter. The following code example shows a
DO
/
UNTIL
loop that contains three instructions and iterates 30 times.
LCNTR = 30, DO the_end UNTIL LCE; /*Loop iterates 30 times*/
R0 = DM(I0,M0), F2 = PM(I8,M8);
R1 = R0-R15;
the_end: F4 = F2 + F3; /*Last instruction in loop*/
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...