FIFO Control and Status
11-14
ADSP-2126x SHARC Processor Hardware Reference
FIFO Control and Status
Several bits can be used to control and monitor FIFO operations:
•
IDP Enable.
The
IDP_ENABLE
bit (bit 7 of the
IDP_CTL
register)
enables the IDP.
•
IDP Buffer Hang Disable.
The
IDP_BHD
bit (bit 4 in the
IDP_CTL
register) determines whether or not the core hangs on reads when
the FIFO is empty.
•
Number of Samples in FIFO.
The
IDP_FIFOSZ
bits (bits 31–28 in
the
DAI_STAT
register) monitors the number of valid data words in
the FIFO.
•
FIFO Overflow Status.
The
IDP_FIFO_OVER
bit (bit 25 in the
DAI_STAT
register) monitors overflow error conditions in the FIFO.
•
FIFO Overflow Clear bit.
The
IDP_CLROVR
bit (bit 6 of the
IDP_CTL
register) clears an indicated FIFO overflow error.
The IDP is enabled through the
IDP_ENABLE
bit. When this bit is set (= 1),
the IDP is enabled. When this bit is cleared (= 0), the IDP is disabled, and
data can not come to the
IDP_FIFO
register from the IDP channels. When
this bit transitions from 1 to 0, all data in the IDP FIFO is cleared.
The
IDP_BHD
bit is used for buffer hang disable control. When there is no
data in the FIFO, reading the
IDP_FIFO
register causes the core to hang.
This condition continues until the FIFO contains valid data. Setting the
IDP_BHD
bit (= 1) prevents the core from hanging on reads from an empty
IDP_FIFO
register. Clearing this bit (= 0) causes the core to hang under the
conditions described previously.
The
IDP_FIFOSZ
bits track the number of words in the FIFO. This
four-bit field identifies the number of valid data samples in the IDP
FIFO.
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...