
Internal Memory Access Listings
5-44
ADSP-2126x SHARC Processor Hardware Reference
32-Bit Normal Word Addressing of Single-Data in
SIMD Mode
shows the SIMD, single-data, normal word addressed access
mode. For normal word addressing, the processor treats the data buses as
two 32-bit normal word lanes. The explicitly addressed (named in the
instruction) 32-bit value completes a transfer using the least significant
normal word lane of the PM or DM data bus. The implicitly addressed
(not named in the instruction, but inferred from the address in SIMD
mode) normal word value completes a transfer using the most significant
normal word lane of the PM or DM data bus.
In
, the explicit access targets the named register
RX
, and the
implicit access targets that register’s complementary register,
SX
. This
instruction uses a
PEx
register with an
RX
mnemonic. If the syntax named
the
PEy
register
SX
as the explicit target, the processor would use that regis-
ter’s complement,
RX
, as the implicit target. For more information on
complementary registers, see
“Secondary Processor Element (PEy)” on
.
shows the data path for one transfer. The processor accesses
normal words sequentially in memory. For more information on arranging
data in memory to take advantage of this access pattern, see
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...