ADSP-2126x SHARC Processor Hardware Reference
9-23
Serial Ports
transfer mode. Clear
SDEN_A
or
SDEN_B
(=0) to disable DMA and set the
channel in an interrupt-driven data transfer mode.
Interrupt-Driven Data Transfer Mode
Both the A and B channels share a common interrupt vector in the inter-
rupt-driven data transfer mode, regardless of whether they are configured
as a transmitter or receiver.
The SPORT generates an interrupt when the transmit buffer has a
vacancy or the receive buffer has data. To determine the source of an
interrupt, applications must check the transmit or receive data buffer sta-
tus bits.
For more information, see “Single Word Transfers” on page -73.
DMA-Driven Data Transfer Mode
Each transmitter and receiver has its own DMA registers. For details, see
“Selecting Transmit and Receive Channel Order (FRFS)” on page 9-16
and
“Moving Data Between SPORTS and Internal Memory” on
. The same DMA channel drives the left and right I
2
S channels
for the transmitter or the receiver. The software application must stop
multiplexing the left and right channel data received by the receive buffer,
because the left and right data is interleaved in the DMA buffers.
Channel A and B on each SPORT share a common interrupt vector. The
DMA controller generates an interrupt at the end of DMA transfer only.
shows the relationship between frame sync (word select), serial
clock, and I
2
S data. Timing for word select is the same as for frame sync.
The
SPL
bit applies to DSP Standard Serial and I
2
S modes only.
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...