
Secondary Processing Element (PEy)
2-50
ADSP-2126x SHARC Processor Hardware Reference
Dual Alternate Registers
Both register files consist of a primary set of 16 by 40-bit registers and an
alternate set of 16 by 40-bit registers. Context switching between the two
sets of registers occurs in parallel between the two processing elements.
For more information, see “Alternate (Secondary) Data Registers” on
page 2-40.
SIMD and Status Flags
When the DSP is in SIMD mode (
PEYEN
bit=1), computations on both
processing elements generate status flags, producing a logical ORing of the
exception status test on each processing element. If one of the four
fixed-point or floating-point exceptions is enabled, an exception condition
on either or both processing elements generates an exception interrupt.
Interrupt service routines (ISRs) must determine which of the processing
elements encountered the exception.
Note that returning from a floating-point interrupt does not automatically
clear the
STKY
state. Code must clear the
STKY
bits in both processing ele-
ment’s sticky status (
STKYx
and
STKYy
) registers as part of the exception
service routine.
“Interrupts and Sequencing” on page 3-48
.
SIMD (Computational) Operations
In SIMD mode, the dual processing elements execute the same instruc-
tion, but operate on different data. To support SIMD operation, the
elements support a variety of dual data move features.
The DSP supports unidirectional and bidirectional register-to-register
transfers with the Conditional Compute and Move instruction. All four
combinations of inter-register file and intra-register file transfers
(PEx
PEx, PEx
PEy, PEy
PEx, and PEy
PEy) are possible in
both SISD (unidirectional) and SIMD (bidirectional) modes.
Summary of Contents for ADSP-21261 SHARC
Page 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Page 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Page 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Page 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Page 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Page 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Page 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Page 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Page 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Page 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Page 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Page 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Page 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...