Renesas H8SX/1650, Руководство по оборудованию

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Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.2.00 Jun. 28, 2007 Page 312 of 666
REJ09B0311-0200
9.3.1 Timer Control Register (TCR)
TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one
for each channel. TCR register settings should be made only while TCNT operation is stopped.
7
CCLR2
0
R/W
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
Bit
Bit Name
Initial Value
R/W
Bit Bit Name
Initial
Value R/W Description
7
6
5
CCLR2
CCLR1
CCLR0
0
0
0
R/W
R/W
R/W
Counter Clear 2 to 0
These bits select the TCNT counter clearing source. See
tables 9.3 and 9.4 for details.
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 1 and 0
These bits select the input clock edge. For details, see
table 9.5. When the input clock is counted using both
edges, the input clock period is halved (e.g. P
φ
/4 both
edges = P
φ
/2 rising edge). If phase counting mode is
used on channels 1, 2, 4, and 5, this setting is ignored
and the phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is P
φ
/4
or slower. This setting is ignored if the input clock is P
φ
/1,
or when overflow/underflow of another channel is
selected.
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Timer Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 9.6 to 9.11 for details. To select the external
clock as the clock source, the DDR bit and ICR bit for the
corresponding pin should be set to 0 and 1, respectively.
For details, see section 8, I/O Ports.