Renesas H8SX/1650, Руководство по оборудованию

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Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 209 of 666
REJ09B0311-0200
6.11.3 Transition Timing
Figure 6.39 shows the timing for transition to the bus released state.
B
φ
Address bus
CSn
LHWR
,
LLWR
AS
Hi-Z
Hi-Z
[1] [2] [3] [4] [7] [5] [6] [8]
Hi-Z
Hi-Z
Hi-Z
Hi-Z
RD
BREQ
BACK
BREQO
External
access cycle
CPU cycle
External bus released state
Data bus
T
1
T
2
[1] A low level of the
BREQ
signal is sampled at the rising edge of the B
φ
signal.
[2] The bus control signals are driven high at the end of the external access cycle. It takes two cycles or
more after the low level of the
BREQ
signal is sampled.
[3] The
BACK
signal is driven low, releasing bus to the external bus master.
[4] The
BREQ
signal state sampling is continued in the external bus released state.
[5] A high level of the
BREQ
signal is sampled.
[6] The
BREQ
signal is driven high, ending external bus release cycle one cycle later.
[7] When the external space is accessed by an internal bus master during external bus released while the BREQOE
bit is set to 1, the
BREQO
signal goes low.
[8] Normally the
BREQO
signal goes high at the rising edge of the
BACK
signal.
Figure 6.39 Bus Released State Transition Timing