Renesas H8SX/1650, Руководство по оборудованию

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Section 5 Interrupt Controller
Rev.2.00 Jun. 28, 2007 Page 111 of 666
REJ09B0311-0200
5.6.4 Interrupt Response Times
Table 5.4 shows interrupt response times – the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The symbols for execution
states used in table 5.4 are explained in table 5.5.
The stack area in on-chip RAM enables high-speed processing.
Table 5.4 Interrupt Response Times
Normal Mode
*
5
Advanced Mode Maximum Mode
*
5
Execution State
Interrupt
Control
Mode 0 Interrupt
Control
Mode 2 Interrupt
Control
Mode 0 Interrupt
Control
Mode 2 Interrupt
Control
Mode 0 Interrupt
Control
Mode 2
Interrupt priority determination
*
1
3
Number of states until executing
instruction ends
*
2
1 to 19 + 2·S
I
PC, CCR, EXR stacking S
K
to 2·S
K
*
6
2·S
K
S
K
to 2·S
K
*
6
2·S
K
2·S
K
2·S
K
Vector fetch S
h
Instruction fetch *
3
2·S
I
Internal processing *
4
2
Total (using on-chip memory) 10 to 31 11 to 31 10 to 31 11 to 31 11 to 31 11 to 31
Notes: 1. Two states for an internal interrupt.
2. In the case of the MULXS or DIVXS instruction
3. Prefetch after interrupt acceptance or for an instruction in the interrupt handling routine.
4. Internal operation after interrupt acceptance or after vector fetch
5. Not available in this LSI.
6. When setting the SP value to 4n, the interrupt response time is S
K
; when setting to 4n +
2, the interrupt response time is 2·S
K
.