Renesas H8SX/1650, Руководство по оборудованию

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Section 12 Watchdog Timer (WDT)
Rev.2.00 Jun. 28, 2007 Page 439 of 666
REJ09B0311-0200
12.3.2 Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written to this bit, to clear the flag.
7
OVF
0
R/(W) *
6
WT/
IT
0
R/W
5
TME
0
R/W
4

1
R
3

1
R
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Bit Bit Name
Initial
Value R/W Description
7 OVF 0 R/(W) * Overflow Flag
Indicates that TCNT has overflowed in interval timer
mode. Only 0 can be written to this bit, to clear the flag.
[Setting condition]
When TCNT overflows in interval timer mode (changes
from H'FF to H'00)
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically by
the internal reset.
[Clearing condition]
Cleared by reading TCSR when OVF = 1, then writing 0
to OVF
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
6 WT/
IT
0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
When TCNT overflows, an interval timer interrupt
(WOVI) is requested.
1: Watchdog timer mode
When TCNT overflows, the
WDTOVF
signal is output.