Renesas H8SX/1650, Руководство по оборудованию

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Section 13 Serial Communication Interface (SCI)
Rev.2.00 Jun. 28, 2007 Page 463 of 666
REJ09B0311-0200
13.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in
normal mode and smart card interface mode.
•
When SMIF in SCMR = 0
Bit
Bit Name
Initial Value
R/W
7
TDRE
1
R/(W) *
6
RDRF
0
R/(W) *
5
ORER
0
R/(W) *
4
FRE
0
R/(W) *
3
PER
0
R/(W) *
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Note: * Only 0 can be written, to clear the flag.
•
When SMIF in SCMR = 1
Bit
Bit Name
Initial Value
R/W
7
TDRE
1
R/(W) *
6
RDRF
0
R/(W) *
5
ORER
0
R/(W) *
4
ERS
0
R/(W) *
3
PER
0
R/(W) *
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Note: * Only 0 can be written, to clear the flag.
Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):
Bit Bit Name
Initial
Value R/W Description
7 TDRE 1 R/(W) * Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
•
When a TXI interrupt request is issued allowing
DTC to write data to TDR