Renesas H8SX/1650, Руководство по оборудованию

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Section 11 8-Bit Timers (TMR)
Rev.2.00 Jun. 28, 2007 Page 411 of 666
REJ09B0311-0200
Section 11 8-Bit Timers (TMR)
This LSI has two units (unit 0 and unit 1) of an on-chip 8-bit timer module that comprise two 8-bit
counter channels, totaling four channels. The 8-bit timer module can be used to count external
events and also be used as a multifunction timer in a variety of applications, such as generation of
counter reset, interrupt requests, and pulse output with a desired duty cycle using a compare-match
signal with two registers.
Figures 11.1 and 11.2 show block diagrams of the 8-bit timer module (unit 0 and unit 1).
This section describes unit 0 (channels 0 and 1), which has the same functions as the other unit.
11.1 Features
•
Selection of seven clock sources
The counters can be driven by one of six internal clock signals (P
φ
/2, P
φ
/18, P
φ
/32, P
φ
/164,
P
φ
/1024, or P
φ
/8192) or an external clock input.
•
Selection of three ways to clear the counters
The counters can be cleared on compare match A or B, or by an external reset signal.
•
Timer output control by a combination of two compare match signals
The timer output signal in each channel is controlled by a combination of two independent
compare match signals, enabling the timer to output pulses with a desired duty cycle or PWM
output.
•
Cascading of two channels (TMR_0 and TMR_1)
Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the
lower 8 bits (16-bit count mode).
TMR_1 can be used to count TMR_0 compare matches (compare match count mode).
•
Three interrupt sources
Compare match A, compare match B, and overflow interrupts can be requested independently.
•
Generation of trigger to start A/D converter conversion
•
Module stop state specifiable