Renesas H8SX/1650, Руководство по оборудованию

Страница: 168 / 692

Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 146 of 666
REJ09B0311-0200
6.4 Multi-Clock Function and Number of Access Cycles
The internal functions of this LSI operate synchronously with the system clock (I
φ
), the peripheral
module clock (P
φ
), or the external bus clock (B
φ
). Table 6.1 shows the synchronization clock and
their corresponding functions.
Table 6.1 Synchronization Clocks and Their Corresponding Functions
Synchronization Clock Function Name
I
φ
MCU operating mode
Interrupt controller
Bus controller
CPU
DTC
Internal memory
Clock pulse generator
Power down control
P
φ
I/O ports
TPU
PPG
TMR
WDT
SCI
A/D
D/A
B
φ
External bus interface
The frequency of each synchronization clock (I
φ
, P
φ
, and B
φ
) is specified by the system clock
control register (SCKCR) independently. For further details, see section 17, Clock Pulse
Generator.
There will be cases when P
φ
and B
φ
are equal to I
φ
and when P
φ
and B
φ
are different from I
φ
according to the SCKCR specifications. In any case, access cycles for internal peripheral functions
and external space is performed synchronously with P
φ
and B
φ
, respectively.
For example, in an external address access where the frequency rate of I
φ
and B
φ
is n : 1, the
operation is performed in synchronization with B
φ
. In this case, external 2-state access space is 2n
cycles and external 3-state access space is 3n cycles (no wait cycles is inserted) if the number of
access cycles is counted based on I
φ
.