Renesas H8SX/1650, Руководство по оборудованию

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Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 213 of 666
REJ09B0311-0200
6.14 Bus Arbitration
This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). This LSI
incorporates internal access and external access bus arbiters that can be used and controlled
independently. The internal bus arbiter handles the CPU and DTC accesses. The external bus
arbiter handles the external access by the CPU and DTC and external bus release request (external
bus master).
The bus arbiters determine priorities at the prescribed timing, and permit use of the bus by means
of the bus request acknowledge signal.
6.14.1 Operation
The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master. If there are bus requests from more than one bus
master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus
master receives the bus request acknowledge signal, it takes possession of the bus until that signal
is canceled.
The priority of the internal bus arbitration:
(High) DTC > CPU (Low)
The priority of the external bus arbitration:
(High) External bus release request > External access by the CPU and DTC (Low)
If the DTC accesses continue, the CPU can be given priority over the DTC to execute the bus
cycles alternatively between them by setting the IBCCS bit in BCR2.
An internal bus access by internal bus masters and external bus release can be executed in parallel.