Renesas H8SX/1650, Руководство по оборудованию

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Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 139 of 666
REJ09B0311-0200
6.2.8 Bus Control Register 2 (BCR2)
BCR2 is used for bus arbitration control of the CPU and DTC, and enabling/disabling of the write
data buffer function to the peripheral modules.
Bit
Bit Name
Initial Value
R/W
7

0
R
6

0
R
5

0
R/W
4
IBCCS
0
R/W
3

0
R
2

0
R
1

1
R/W
0
PWDBE
0
R/W
Bit Bit Name
Initial
Value R/W Description
7, 6

All 0 R Reserved
These are read-only bits and cannot be modified.
5

0 R/W Reserved
This bit is always read as 0. The write value should
always be 0.
4 IBCCS 0 R/W Internal Bus Cycle Control Select
Selects the internal bus arbiter function.
0: Releases the bus mastership according to the priority
1: Executes the bus cycles alternatively when a CPU bus
mastership request conflicts with a DTC bus
mastership request
3, 2

All 0 R Reserved
These are read-only bits and cannot be modified.
1

1 R/W Reserved
This bit is always read as 1. The write value should
always be 1.
0 PWDBE 0 R/W Peripheral Module Write Data Buffer Enable
Specifies whether or not to use the write data buffer
function for the peripheral module write cycles.
0: Write data buffer function not used
1: Write data buffer function used