Renesas H8SX/1650, Руководство по оборудованию

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Section 12 Watchdog Timer (WDT)
Rev.2.00 Jun. 28, 2007 Page 437 of 666
REJ09B0311-0200
Section 12 Watchdog Timer (WDT)
The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (
WDTOVF
) if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At
the same time, the WDT can also generate an internal reset signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
Figure 12.1 shows a block diagram of the WDT.
12.1 Features
•
Selectable from eight counter input clocks
•
Switchable between watchdog timer mode and interval timer mode

In watchdog timer mode
If the counter overflows, the WDT outputs
WDTOVF
. It is possible to select whether or
not the entire LSI is reset at the same time.

In interval timer mode
If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
Overflow
Interrupt
control
WOVI
(interrupt request
signal)
Internal reset signal *
WDTOVF
Reset
control
RSTCSR TCNT TCSR
P
φ
/2
P
φ
/64
P
φ
/128
P
φ
/512
P
φ
/2048
P
φ
/8192
P
φ
/32768
P
φ
/131072
Clock
Clock
select
Internal clocks
Bus
interface
Module bus
TCSR:
TCNT:
RSTCSR:
Note:
*
An internal reset signal can be generated by the RSTCSR setting.
Timer control/status register
Timer counter
Reset control/status register
WDT
[Legend]
Internal bus
Figure 12.1 Block Diagram of WDT