Renesas H8SX/1650, Руководство по оборудованию

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Section 10 Programmable Pulse Generator (PPG)
Rev.2.00 Jun. 28, 2007 Page 401 of 666
REJ09B0311-0200
10.4 Operation
Figure 10.2 shows a schematic diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in NDER are set to 1. An initial output value is determined by its
corresponding PODR initial setting. When the compare match event specified by PCR occurs, the
corresponding NDR bit contents are transferred to PODR to update the output values. Sequential
output of data of up to 16 bits is possible by writing new output data to NDR before the next
compare match.
Output trigger signal
Pulse output pin
Internal data bus
Normal output/inverted output
C
PODR Q D
NDER
Q
NDR Q D
Figure 10.2 Schematic Diagram of PPG
10.4.1 Output Timing
If pulse output is enabled, the NDR contents are transferred to PODR and output when the
specified compare match event occurs. Figure 10.3 shows the timing of these operations for the
case of normal output in groups 2 and 3, triggered by compare match A.
TCNT
N N + 1
P
φ
TGRA N
Compare match
A signal
NDRH
m n PODRH
PO8 to PO15
n
m n
Figure 10.3 Timing of Transfer and Output of NDR Contents (Example)