Renesas H8SX/1650, Руководство по оборудованию

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Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 155 of 666
REJ09B0311-0200
Output waveform
B
φ
Area 5 access
CS6
CS5
Area 6 access
Area 5 access Area 6 access Address bus
Figure 6.9 Timing When
CS
Signal is Output to the Same Pin
6.5.4 External Bus Interface
The type of the external bus interfaces, bus width, endian format, number of access cycles, and
strobe assert/negate timings can be set for each area in the external address space. The bus width
and the number of access cycles for both on-chip memory and internal I/O registers are fixed, and
are not affected by the external bus settings.
(1)
Type of External Bus Interface
Four types of external bus interfaces are provided and can be selected in area units. Table 6.4
shows each interface name, description, and area name to be set for each interface. Table 6.5
shows the areas that can be specified for each interface. The initial state of each area is a basic bus
interface.
Table 6.4 Interface Names and Area Names
Interface Description Area Name
Basic interface Directly connected to ROM and RAM Basic bus space
Byte control SRAM
interface Directly connected to byte SRAM with
byte control pin Byte control SRAM space
Burst ROM interface Directly connected to the ROM that
allows page access Burst ROM space
Address/data multiplexed
I/O interface Directly connected to the peripheral
LSI that requires address and data
multiplexing Address/data multiplexed I/O
space