Renesas H8SX/1650, Руководство по оборудованию

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Section 5 Interrupt Controller
Rev.2.00 Jun. 28, 2007 Page 101 of 666
REJ09B0311-0200
A block diagram of interrupts IRQn is shown in figure 5.2.
IRQn interrupt request
IRQnE
IRQnF
S
R
Q
Clear signal
Edge/level
detection circuit
Input buffer
Corresponding bit
in ICR
IRQnSF, IRQnSR
IRQn
input
[Legend]
n = 14 to 0
Figure 5.2 Block Diagram of Interrupts IRQn
When the IRQ sensing control in ISCR is set to a low level of signal
IRQn
, the level of
IRQn
should be held low until an interrupt handling starts. Then set the corresponding input signal
IRQn
to high in the interrupt handling routine and clear the IRQnF to 0. Interrupts may not be executed
when the corresponding input signal
IRQn
is set to high before the interrupt handling begins.
5.4.2 Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features:
•
For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that enable or disable these interrupts. They can be controlled independently.
When the enable bit is set to 1, an interrupt request is issued to the interrupt controller.
•
The interrupt priority can be set by means of IPR.
•
The DTC can be activated by a TPU, SCI, or other interrupt request.
•
DTC activation can be controlled by the CPU priority control enable and DTC priority bits.