Renesas H8SX/1650, Руководство по оборудованию

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Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 210 of 666
REJ09B0311-0200
6.12 Internal Bus
6.12.1 Access to Internal Address Space
The internal address spaces of this LSI are the on-chip RAM space and register space for the on-
chip peripheral modules. The number of cycles necessary for access differs according the space.
Table 6.25 shows the number of access cycles for each on-chip memory space.
Table 6.25 Number of Access Cycles for On-Chip Memory Spaces
Access Space Access Number of Access Cycles
Read One I
φ
cycle On-chip RAM space
Write One I
φ
cycle
In access to the registers for on-chip peripheral modules, the number of access cycles differs
according to the register to be accessed. When the dividing ratio of the operating clock of a bus
master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0
to n-1 are inserted for register access in the same way as for external bus clock division.
The number of access cycles to the registers for on-chip peripheral modules is shown in table 6.26.
Table 6.26 Number of Access Cycles for Registers of On-Chip Peripheral Modules
Number of Cycles
Module to be Accessed Read Write Write Data Buffer Function
MCU operating mode, clock pulse
generator, power-down control registers,
interrupt controller, bus controller, and DTC
registers 2I
φ
3I
φ
Disabled
I/O port PFCR registers and WDT registers 2P
φ
3P
φ
Disabled
I/O port registers other than PFCR, TPU,
PPG, TMR, SCI, A/D, and D/A registers 2P
φ
Enabled