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M0A21/M0A23 Series
May 06, 2022
Page
363
of 746
Rev 1.02
M0
A21
/M
0
A
2
3
SE
RIES
TEC
H
NICAL
RE
FEREN
C
E
M
ANUAL
Note:
n denotes 0 to 5
8
7
6
5
4
3
2
1
8
7
6
5
PWM counter
1
7
Capture Input
PWM_FCAPDATn
5
PWM_RCAPDATn
Capture interrupt
CAPFIENn
CAPRIENn
CAPINENn
Clear by S/W
CFLIFn
CRLIFn
Reload (PERIOD = 8)
Reload
Clear by S/W
Falling Latch
Falling Latch
Rising Latch
FCRLDENn
RCRLDENn
Figure 6.10-35 Capture Operation Waveform
The capture pulse width meeting the following conditions can be calculated according to the formula.
1. The capture positive or negative pulse width is shorter than a counter period.
2. The counter operates in down counter type.
3.
The counter can be reloaded by both falling and rising capture events through setting FCRLDENn
and RCRLDENn bits of PWM_CAPCTL register to 1.
For the negative pulse case, the channel low pulse width is calculated as (PWM_PERIODn + 1 -
PWM_RCAPDATn) PWM counter time, where one PWM counter time is (1) * PWMx_CLK
clock time. In Figure 6.10-35, the low pulse width is 8+1-5 = 4 PWM counter time.
For the positive pulse case, the channel high pulse width is calculated as (PWM_PERIODn + 1 -
PWM_FCAPDATn) PWM counter time, where one PWM counter time is (1) * PWMx_CLK
clock time. In Figure 6.10-35, the high pulse width is 8+1-7 = 2 PWM counter time.
6.10.5.25 Capture PDMA Function
The PWM module supports the PDMA transfer function when operating in the capture mode (
Note:
If
the PDMA function is not supported, this bit field will become invalid. Please refer to section 3.2
NuMicro
®
M0A21/M0A23 Series Selection Guide for detailed information.). When the corresponding
PDMA enable bit CHENn_m (CHEN0_1 at PWM_PDMACTL[0], CHEN2_3 at PWM_PDMACTL[8] and
CHEN4_5 at PWM_PDMACTL[16], where n and m denote complement pair channels) is set, the capture