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M0A21/M0A23 Series
May 06, 2022
Page
194
of 746
Rev 1.02
M0
A21
/M
0
A
2
3
SE
RIES
TEC
H
NICAL
RE
FEREN
C
E
M
ANUAL
APB Devices Clock Enable Control Register 1 (CLK_APBCLK1)
The bits in this register are used to enable/disable clock for peripheral controller clocks.
Register
Offset
R/W Description
Reset Value
CLK_APBCLK1
0x0C
R/W APB Devices Clock Enable Control Register 1
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
PWM0CKEN
15
14
13
12
11
10
9
8
Reserved
DACCKEN
Reserved
USCI1CKEN
USCI0CKEN
7
6
5
4
3
2
1
0
Reserved
Bits
Description
[31:17]
Reserved
Reserved.
[16]
PWM0CKEN
PWM0 Clock Enable Bit
0 = PWM0 clock Disabled.
1 = PWM0 clock Enabled.
[15:13]
Reserved
Reserved.
[12]
DACCKEN
DAC Clock Enable Bit
0 = DAC clock Disabled.
1 = DAC clock Enabled.
[11:10]
Reserved
Reserved.
[9]
USCI1CKEN
USCI1 Clock Enable Bit
0 = USCI1 clock Disabled.
1 = USCI1 clock Enabled.
[8]
USCI0CKEN
USCI0 Clock Enable Bit
0 = USCI0 clock Disabled.
1 = USCI0 clock Enabled.
[7:0]
Reserved
Reserved.