NEC ?PD703302, Руководство пользователя

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
User’s Manual U16896EJ2V0UD
208
(c) Processing of overflow when two capture registers are used
Care must be exercised in processing the overflow flag when two capture registers are used. First, an
example of incorrect processing is shown below.
Example of incorrect processing when two capture registers are used
FFFFH
16-bit counter
0000H
TP0CE bit
TIP00 pin input
TP0CCR0 register
TIP01 pin input
TP0CCR1 register
INTTP0OV signal
TP0OVF bit
D
00
D
01
D
10
D
11
D
10
<1> <2> <3> <4>
D
00
D
11
D
01
The following problem may occur when two pulse widths are measured in the free-running timer mode.
<1> Read the TP0CCR0 register (setting of the default value of the TIP00 pin input).
<2> Read the TP0CCR1 register (setting of the default value of the TIP01 pin input).
<3> Read the TP0CCR0 register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by ( D
01
−
D
00
).
<4> Read the TP0CCR1 register.
Read the overflow flag. Because the flag is cleared in <3>, 0 is read.
Because the overflow flag is 0, the pulse width can be calculated by (D
11
−
D
10
) (incorrect).
When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the
other capture register may not obtain the correct pulse width.
Use software when using two capture registers. An example of how to use software is shown below.