NEC ?PD703302, Руководство пользователя

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CHAPTER 16 I
2
C BUS
User’s Manual U16896EJ2V0UD
474
(4) IIC clock selection register 0 (IICCL0)
The IICCL0 register is used to set the transfer clock for I
2
C0.
The IICCL0 register can be read or written in 8-bit or 1-bit units. However, the CLD0 and DAD0 bits are read-
only. The SMC0, CL01, and CL00 bits are set in combination with the IICX0.CLX0 bit (refer to 16.3 (6) I
2
C0
transfer clock setting method ).
Set the IICCL0 register when the IICC0.IICE0 bit = 0.
Reset sets this register to 00H.
After reset: 00H R/W
Note
Address: FFFFFD84H
7 6 <5> <4> 3 2 1 0
IICCL0 0 0 CLD0 DAD0 SMC0 DFC0 CL01 CL00
CLD0 Detection of SCL0 pin level (valid only when IICC0.IICE0 bit = 1)
0 The SCL0 pin was detected at low level.
1 The SCL0 pin was detected at high level.
Condition for clearing (CLD0 bit = 0) Condition for setting (CLD0 bit = 1)
•
When the SCL0 pin is at low level
•
When the IICE0 bit changes from 1 to 0 (operation stop)
•
Reset
•
When the SCL0 pin is at high level
DAD0 Detection of SDA0 pin level (valid only when IICE0 bit = 1)
0 The SDA0 pin was detected at low level.
1 The SDA0 pin was detected at high level.
Condition for clearing (DAD0 bit = 0) Condition for setting (DAD0 bit = 1)
•
When the SDA0 pin is at low level
•
When the IICE0 bit changes from 1 to 0 (operation stop)
•
Reset
•
When the SDA0 pin is at high level
SMC0 Operation mode switching
0 Operates in standard mode.
1 Operates in high-speed mode.
DFC0 Digital filter operation control
0 Digital filter off.
1 Digital filter on.
Digital filter can be used only in high-speed mode.
In high-speed mode, the transfer clock does not vary regardless of DFC0 bit set/clear.
The digital filter is used for noise elimination in high-speed mode.
Note Bits 4 and 5 are read-only bits.
<R>