CHAPTER 3 CPU FUNCTION
78
User’s Manual U15195EJ5V0UD
3.4.9 Specific
registers
Specific registers are registers that are protected from being written with illegal data due to inadvertent program
loop (runaway), etc. The V850E/IA2 has three specific registers, the power save control register (PSC) (refer to
8.5.2
(3) Power save control register (PSC)
), clock control register (CKC) (refer to
8.3.4 Clock control register (CKC)
),
and flash programming mode control register (FLPMC) (refer to
15.7.12 Flash programming mode control register
(FLPMC)
).
3.4.10 System wait control register (VSWC)
The system wait control register (VSWC) controls the wait cycles of a bus access to the on-chip peripheral I/O
registers.
Set the following values to this register.
Set value of VSWC: 02H (when two wait clocks are set, with operating frequency (f
XX
) = 40 MHz)
This register can be read/written in 8-bit units (address: FFFFF06EH, after reset: 77H).
Remark
If the timing at which the flag or count value changes overlaps the register access timing when a register
that includes a status flag indicating the status of on-chip peripheral functions (ASIF0, etc.) or a register
that indicates a timer count value (TM0n, etc.) are accessed, a register access retry operation occurs.
Therefore, it may take longer than normal to access an on-chip peripheral register.
3.4.11 Cautions
(1) Register to be set first
When using the V850E/IA2, the following registers must be set from the beginning.
•
System wait control register (VSWC)
(See
3.4.10 System wait control register (VSWC)
)
•
Clock control register (CKC)
(See
8.3.4 Clock control register (CKC)
)
After setting VSWC and CKC, set other registers as required.
Содержание PD703114
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