NEC PD703114, Руководство пользователя

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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
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User’s Manual U15195EJ5V0UD
Figure 6-8 shows the configuration of the buffer register.
Figure 6-8. Buffer Register Configuration
The actual DMA transfer is performed based on the settings of the slave register.
The settings incorporated in the master and slave registers differ as follows according to the timing (time) at which
the settings were made.
(1) Time from system reset to the generation of the first DMA transfer request
The settings made are incorporated in both the master and slave registers.
(2) During DMA transfer (time from the generation to end of DMA transfer request)
The settings made are incorporated in only the master register, and not in the slave register (the slave
register maintains the value set for the next DMA transfer).
However, the contents of the master register are automatically overwritten in the slave register after DMA
transfer ends.
If the value of each register is read during this period, the value of the slave register is read.
To check that DMA transfer has been started, confirm that the first transfer has been executed by reading the
DBCn register (n = 0 to 3).
(3) Time from DMA transfer end to the start of the next DMA transfer
The settings made are incorporated in both the master and slave registers.
Remark “DMA transfer end” means one of the following.
•
Completion of DMA transfer (terminal count)
•
Forcible termination of DMA transfer (the INITn bit of the DCHCn register is set to 1)
Data read
Data write
Master
register
Slave
register
Address/
count
controller
Internal bus