CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
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User’s Manual U15195EJ5V0UD
6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n (n = 0 to 3).
These registers can be read/written in 8-bit or 1-bit units. (However, bit 7 is read only and bits 2 and 1 are write
only. If bits 2 and 1 are read, the read value is always 0.)
Be sure to set bits 6 to 4 to 0. If they are set to 1, the operation is not guaranteed.
Cautions 1. If transfer is completed with the MLEn bit set to 1, and the next transfer request is executed
with the DMA transfer (hardware DMA) started by an interrupt from the on-chip peripheral I/O,
the next transfer will be executed if the TCn bit is set to 1 (will not be automatically cleared to
0).
2. Set the MLEn bit when the corresponding channel is in one of the following periods (the
operation is not guaranteed if set at another timing).
•
Time from system reset to the generation of the first DMA transfer request
•
Time from DMA transfer end (after terminal count) to the generation of the next DMA
transfer request
•
Time from the forcible termination of DMA transfer (after the INITn bit has been set to 1) to
the generation of the next DMA transfer request
3. If DMA transfer is forcibly terminated in the last transfer cycle with the MLEn bit set to 1, the
same operations as transfer completion (setting of the TCn bit to 1) are performed (the Enn
bit will be cleared to 0 in forcible termination regardless of the value of the MLEn bit).
In this case, at the next DMA transfer request, the Enn bit must be set to 1 and the TCn bit
must be read (cleared to 0).
4. During DMA transfer completion (terminal count), each bit is updated in the order of clearing
the Enn bit to 0 and setting the TCn bit to 1. For this reason, if the TCn bit and Enn bit are in
the polling mode, the value indicating “transfer not completed, and transfer prohibited” (TCn
bit = 0, and Enn bit = 0) may be read in some cases if the DCHCn register is read while each
of the above bits is being updated (this is not an error).
5. Do not set the Enn and STGn bits while DMA is suspended. The operation is not guaranteed
if set while DMA is suspended.
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