684
User's Manual U15195EJ5V0UD
APPENDIX D REVISION HISTORY
D.1 Major Revisions in This Edition
(1/2)
Page Description
Throughout
•
Addition of the following lead-free products
µ
PD703114GC-xxx-8EU-A, 703114GC(A)-xxx-8EU-A,
703114GF-xxx-3BA-A, 70F3114GC-8EU-A,
70F3114GC(A)-8EU-A, 70F3114GF-3BA-A
•
Addition of FLPMC register
p. 18
Addition of
Note
to
Table 1-1 Differences Between V850E/IA1 and V850E/IA2
p. 19
Change of number of instructions in
1.2 Features
p. 49
Addition of
Note
to
Table 3-2 System Register Numbers
pp. 50, 51,
53, 54
Addition of
3.2.2 (1) Interrupt status saving registers (EIPC, EIPSW)
,
(2) NMI status saving registers (FEPC,
FEPSW)
,
(5) CALLT execution status saving registers (CTPC, CTPSW)
,
(6) Exception/debug trap status
saving registers (DBPC, DBPSW)
, and
(7) CALLT base pointer (CTBP)
p. 79
Addition of
3.4.11 (2) Restriction on conflict between sld instruction and interrupt request
pp. 114, 115 Modification of description in
6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
p. 116
Modification of description in
6.3.7 DMA restart register (DRST)
pp. 117, 119 Modification of description and addition of
Caution
to
6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to
DTFR3)
p. 123
Addition of
Figure 6-7 Block Transfer Example
p. 123
Modification of description of
Caution
in
6.5.1 Two-cycle transfer
p. 124
Addition of
Note
to
Table 6-1 Relationship Between Transfer Type and Transfer Target
p. 125
Deletion of a part of description in
6.7 DMA Channel Priorities
pp. 125, 126 Modification of description in
6.8 Next Address Setting Function
p. 129
Addition of
Figure 6-9 Example of Forcible Termination of DMA Transfer
p. 132
Modification of descriptions in
6.14 (2) Transfer of misaligned data
and
(4) DMA start factors
p. 132
Addition of
6.14 (5) Program execution and DMA transfer with internal RAM
p. 134
Addition of
Caution
to
7.1 Features
pp. 135, 137 Addition of
Note
and
Remark
to
Table 7-1 Interrupt/Exception Source List
p. 160
Addition of
Caution
to
7.3.8 (4) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5)
p. 169
Addition of
Caution
to
7.5.2 (2) Restore
p. 173
Modification of description in
7.8 Periods in Which CPU Does Not Acknowledge Interrupts
p. 185
Modification of description in
8.5.2 (3) Power save control register (PSC)
p. 189
Addition of description to
Table 8-4 Operation Status in IDLE Mode
p. 190
Addition of
Caution
to
8.5.4 (2) (a) Release by a non-maskable interrupt request or an unmasked maskable
interrupt request
p. 191
Addition of description to
Table 8-6 Operation Status in Software STOP Mode
p. 192
Addition of
Caution
to
8.5.5 (2) (a) Release by a non-maskable interrupt request or an unmasked maskable
interrupt request
p. 279
Addition of
9.1.6 (4) [Output waveform width with respect to set value] (d) When BFCMnx = 0000H is set
while DTMnx = 000H or TM0CEDn bit = 1
p. 281
Addition of
9.1.6 (4) [Output waveform width with respect to set value] (e) When BFCMnx = CM0n3 = a is set
p. 297
Addition of
Caution
to
9.2.3 (1) Timer 10 (TM10)
p. 305
Modification of description in table in
9.2.4 (6) (b) UDC mode (CMD bit of TUM0 register = 1)
p. 313
Modification of description in
Table 9-8 List of Count Operations in UDC Mode
Содержание PD703114
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