NEC PD703114, Руководство пользователя

Страница: 495 / 692

CHAPTER 10 SERIAL INTERFACE FUNCTION
User’s Manual U15195EJ5V0UD
495
(b) Clock phase selection
The following shows the timing when changing the conditions for clock phase selection (CKP bit of
CSICn register) and data phase selection (DAP bit of CSICn register) under the following conditions.
•
Data length = 8 bits (CCL bit of CSIMn register = 0)
•
First bit of transfer data = MSB (DIRn bit of CSIMn register = 0)
•
No interrupt request signal delay control (CSIT bit of CSIMn register = 0)
Figure 10-28. Timing Chart According to Clock Phase Selection (1/2)
(a) When CKP bit = 0, DAP bit = 0
DI7 DI6 DI5 DI4 DI3 DI2 DI1
DO7 DO6 DO5 DO4 DO3 DO2 DO1
SCKn (I/O)
SIn (input)
SOn (output)
Reg_R/W
INTCSIn interrupt
CSOTn bit
DI0
DO0
(b) When CKP bit = 1, DAP bit = 0
DI7 DI6 DI5 DI4 DI3 DI2 DI1
DO7 DO6 DO5 DO4 DO3 DO2 DO1
SCKn (I/O)
SIn (input)
SOn (output)
Reg_R/W
INTCSIn interrupt
CSOTn bit
DI0
DO0
Remarks 1. n = 0, 1
2. Reg_R/W: Internal signal. This signal indicates that receive data buffer register (SIRBn/
SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was
performed .