NEC PD703114, Руководство пользователя

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CHAPTER 9 TIMER/COUNTER FUNCTION
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User’s Manual U15195EJ5V0UD
(3) Cycle measurement
By setting the TMC30 and TMC31 registers as shown in Figure 9-100, timer 3 can measure the cycle of
signals input to the INTP30 pin or INTP31 pin.
The valid edge of the INTP30 pin is selected according to the IES301 and IES300 bits of the SESC register,
and the valid edge of the INTP31 pin is selected according to the IES311 and IES310 bits of the SESC
register. Either the rising edge, the falling edge, or both edges can be selected as the valid edges of both
pins.
If the CC30 register is set to a capture register and TM3 is started, the valid edge input of the INTP30 pin is
set as the trigger for capturing the TM3 register value in the CC30 register. When this value is captured, an
INTCC30 interrupt is generated.
Similarly, if the CC31 register is set to a capture register and TM3 is started, the valid edge input of the
INTP31 pin is set as the trigger for capturing the TM3 register value in the CC31 register. When this value is
captured, an INTCC31 interrupt is generated.
The cycle of signals input to the INTP30 pin is calculated by obtaining the difference between the TM3
register’s count value (Dx) that was captured in the CC30 register according to the x-th valid edge input of the
INTP30 pin and the TM3 register’s count value (D(x+1)) that was captured in the CC30 register according to
the (x+1)-th valid edge input of the INTP30 pin and multiplying the value of this difference by the cycle of the
clock control signal.
The cycle of signals input to the INTP31 pin is calculated by obtaining the difference between the TM3
register’s count value (Dx) that was captured in the CC31 register according to the x-th valid edge input of the
INTP31 pin and the TM3 register’s count value (D(x+1)) that was captured in the CC31 register according to
the (x+1)-th valid edge input of the INTP31 pin and multiplying the value of this difference by the cycle of the
clock control signal.
Figure 9-100. Contents of Register Settings When Timer 3 Is Used for Cycle Measurement
Supply input clocks to internal units
Enable count operation
0 0/1 0/1 0/1 0/1 0/1 0 0
OST ENT1 ALV ETI CCLR CMS1 CMS0
0/1 0/1 0/1 0/1 0 0 1 1
TM3OVF
TMC30
TMC31
CS2 CS1 CS0 TM3CE TM3CAE
Use CC30 register as capture register
(when measuring the cycle of INTP30 input)
Use CC31 register as capture register
(when measuring the cycle of INTP31 input)
Continue counting after TM3 register
overflows
ECLR
Remark 0/1: Set to 0 or 1 as necessary